AXI BARs Tab - AXI BARs Tab - 3.0 English - PG194

AXI Bridge for PCI Express Gen3 Subsystem Product Guide (PG194)

Document_ID
PG194
Release_Date
2025-11-20
Version
3.0 English

The AXI Base Address Registers (BARs) parameters shown in the following figure set the AXI base address registers and the translation between AXI Memory space and PCI Express® Memory space. Each BAR has a Base Address, High Address, and translation field which can be configured through the Vivado IDE.

Figure 1. AXI Base Address Registers

Number of BARs
Indicates the number of AXI BARs enabled. The BARs are enabled sequentially.
Aperture Base Address
Sets the base address for the address range of BAR. You should edit this parameter to fit design requirements.

In the AMD Vivado™ IDE, this parameter is handled in the Address Manager, and does not appear in the Core Customization dialog box.

Aperture High Address
Sets the upper address threshold for the address range of BAR. You should edit this parameter to fit design requirements.

In the Vivado IDE, this parameter is handled in the Address Manager, and does not appear in the Core Customization dialog box.

AXI to PCIe Translation
Configures the translation mapping between AXI and PCI Express address space. You should edit this parameter to fit design requirements.