Wizard Basic Concepts - 1.7 English

UltraScale FPGAs Transceivers Wizard LogiCORE IP Product Guide (PG182)

Document ID
PG182
Release Date
2023-05-17
Version
1.7 English

Transceiver primitives . Fundamentally, the wizard instantiates, configures, and connects one or more serial transceiver primitives to provide a simplified user interface to those resources. The core instance configures the channel and common primitives by applying HDL parameter values derived from the AMD Vivado Integrated Design Environment (IDE)-driven customization of that instance.

Transceiver configuration presets . During Vivado IDE-driven customization, you can choose from a variety of transceiver configuration presets to target an industry standard. If required, customization settings can be further modified to suit your application.

Optional port enablement . AMD serial transceiver primitives have many ports, and most ports are usually not required for any one mode use. The wizard provides access to all transceiver primitive ports using an optional port enablement interface, but by default offers a compact user interface by exposing only those ports likely to be necessary for the core as customized. Some of the ports might not be applicable to be exposed from GT wizard core due to the customization and optional enablement of some of the helper cores.

Helper blocks . The wizard provides optional modules called helper blocks that abstract or automate certain common or complex transceiver usage procedures. Each helper block can be located either within the core or outside it. They are delivered with the example design as a user-modifiable starting point. Helper blocks in this release include:

Reset controller . Controls and abstracts the transceiver reset sequence.

Transmitter user clocking network . Contains resources to drive the transmitter user clocking network.

Receiver user clocking network . Contains resources to drive the receiver user clocking network.

User data width sizing . Sizes the transmitter and receiver data vectors to the specified user widths.

Transmitter buffer bypass controller . Controls and abstracts the transmitter buffer bypass procedure, if required.

Receiver buffer bypass controller . Controls and abstracts the receiver buffer bypass procedure, if required.


The wizard is intended to simplify the use of serial transceivers. However, it is still important to understand the behavior, usage, and limitations of the transceivers. See the UltraScale Architecture GTH Transceivers User Guide (UG576) [Ref 1] or UltraScale Architecture GTY Transceivers User Guide (UG578) [Ref 2] for details.

This Figure and its description illustrate the basic concepts of the wizard in the context of the core hierarchy.

Figure: Wizard IP Core Block Diagram

Page-1 Sheet.1 IP Core Wrapper IP Core Wrapper Sheet.2 Top-level HDL Sheet.3 Sheet.4 Top-level HDL Sheet.5 Sheet.6 Transceiver CHANNEL Wrapper Sheet.7 Sheet.8 TransceiverCHANNEL Wrapper Sheet.9 Sheet.10 Sheet.11 Sheet.12 Sheet.13 Sheet.14 Sheet.15 CHANNEL Primitive CHANNELPrimitive Sheet.16 Sheet.17 Sheet.18 Sheet.19 Sheet.20 Sheet.21 Sheet.22 Optional Helper Block 2 OptionalHelper Block 2 Sheet.23 Optional Helper Block 1 OptionalHelper Block 1 Sheet.24 Sheet.25 Sheet.26 Sheet.27 Sheet.28 Sheet.29 Sheet.30 Sheet.31 B B Sheet.32 C C Sheet.33 D D Sheet.34 B’ B’ Sheet.35 A’ A’ Sheet.36 Transceiver COMMON Wrapper Sheet.37 Sheet.38 TransceiverCOMMON Wrapper Sheet.39 Sheet.40 Sheet.41 Sheet.42 Sheet.43 Sheet.44 Sheet.45 COMMON Primitive COMMONPrimitive Sheet.46 Sheet.47 Sheet.48 Sheet.49 Sheet.50 Sheet.51 Sheet.52 A A Sheet.53 X14538 X14538 Sheet.54 Sheet.55 Sheet.56 Sheet.57 Sheet.58 curve.484 curve.20 Sheet.61 Sheet.62

Transceiver channel primitives and transceiver common primitives are instantiated by the transceiver channel wrapper and transceiver common wrapper modules, respectively. One or more wrapper modules can be used to instantiate those transceiver primitives as required for your application. The wrapper modules apply appropriate parameter values to the underlying transceiver primitives based on the choices made during IP customization, or according to the selected transceiver configuration preset. These wrappers, like the rest of the core hierarchy, should not be user-modified.

To provide a compact user interface, only those transceiver primitive ports that are likely needed for the selected configuration are exposed as wizard IP core-level ports by default. Input vector A represents an enabled core port that drives a corresponding input port of one or more transceiver channel primitives. Likewise, output vector A' is driven by a corresponding output port of one or more transceiver common primitives. If not enabled by default, user-required ports can be individually enabled during IP customization for maximum flexibility.

Transceiver primitive input ports that are not exposed through the core boundary are tied off to their appropriate values (per the core customization) within the Vivado Design Suite IP core wrapper. Net B represents an input port of one or more transceiver channel primitives that is not enabled as a core port and is automatically tied Low by the wizard. Net B' represents an analogous transceiver common primitive input, tied High.

The wizard provides optional helper blocks to simplify common or complex transceiver usage, and each helper block can be located either within the core or within the user-modifiable example design. Vector C represents the simple user interface of the optional helper blocks when located within the core, while nets D represents the more complex interface between those helper blocks and the transceiver channel and/or common primitives to which they connect.