VIO Core Instance - 1.7 English

To simplify example design hardware bring-up and debug, a VIO core instance is included in the example design top-level module. By default, the instance is adapted to the customized Wizard core to probe key status and debug signals, and to drive key control signals. It can be re-customized and connected to other signals as needed.

The default VIO core instance always probes the following:

• ​ the link status indicator signals link_status_out and link_down_latched_out .

• ​ the initialization module retry counter signals init_done_int and init_retry_ctr_int .

• ​ synchronized versions of reset helper block signals gtwiz_reset_tx_done_out and gtwiz_reset_rx_done_out .

The VIO core always drives the following:

• ​ internal versions (using a logical OR where appropriate) of link status indicator signal link_down_latched_reset_in .

• ​ reset helper block signals gtwiz_reset_all_in , gtwiz_reset_tx_pll_and_datapath_in , gtwiz_reset_tx_datapath_in , gtwiz_reset_rx_pll_and_datapath_in , and gtwiz_reset_rx_datapath_in .

By interacting with these key signals, using the VIO core can reduce reliance on hardware
I/O interaction and provide rapid insight into basic system behavior.

The default VIO core instance probes synchronized versions of the following signals if they are available in the example design top-level module for the customized Wizard core:

TIP: To probe these signals, use the optional ports interface during IP customization to expose the relevant ports through the IP core boundary.

One VIO probe port is used per signal, and each signal is vectored across all enabled transceiver primitives.

The default VIO core instance drives the following signals if they are available in the example design top-level module for the customized Wizard core. Synchronizers are used where appropriate:

TIP: To interactively drive these signals, use the optional ports interface during IP customization to expose the relevant ports through the IP core boundary.

One VIO probe port is used per signal, and each signal is vectored across all enabled transceiver primitives.

To probe additional wizard signals available in the example design top-level module, re-customize the VIO core instance to add further probe ports. For more details on using the VIO core and other Vivado Design Suite debug features, see Vivado Design Suite User Guide: Programming and Debugging (UG908) [Ref 12] .