User Data Width Sizing Helper Block Ports

User Data Width Sizing Helper Block Ports - 1.7 English

UltraScale FPGAs Transceivers Wizard LogiCORE IP Product Guide (PG182)

Document ID

PG182

Release Date

2023-05-17

Version

1.7 English

The user data width sizing helper block consists of two modules. One for the transmitter user data interface and the other for the receiver user data interface. Each module contains a user interface and a transceiver interface. The user interface provides a single vector sized to user data width and scaled by the number of transceiver channels. The transceiver interface implements the bit assignments and any interleaving or de-interleaving required for interfacing to the data transmission and reception ports on the transceiver channel primitives.

User data width sizing helper block user interface ports can be identified by the prefix gtwiz_userdata_. See Designing with the Core , for information about the user data width sizing helper block. The user and transceiver interfaces of the helper block transmitter and receiver modules are described in Table: User Data Width Sizing Helper Block User Interface Ports (Transmitter Module) through Table: User Data Width Sizing Helper Block Transceiver Interface Ports (Receiver Module) .

Table: User Data Width Sizing Helper Block User Interface Ports (Transmitter Module)
Name	Direction	Width	Clock Domain	Description
gtwiz_userdata_tx_in	Input	TX user data width × Num. channels	TXUSRCLK2, per channel	User interface for data to be transmitted by transceiver channels

Table: User Data Width Sizing Helper Block User Interface Ports (Receiver Module)
Name	Direction	Width	Clock Domain	Description
gtwiz_userdata_rx_out	Output	RX user data width × Num. channels	RXUSRCLK2, per channel	User interface for data received by transceiver channels

Table: User Data Width Sizing Helper Block Transceiver Interface Ports (Transmitter Module)
Name	Direction	Width	Clock Domain	Description
txdata_out	Output	128 × Num. channels	TXUSRCLK2, per channel	Connects to TXDATA on transceiver channel primitives
txctrl0_out	Output	16 × Num. channels	TXUSRCLK2, per channel	Connects to TXCTRL0 on transceiver channel primitives
txctrl1_out	Output	16 × Num. channels	TXUSRCLK2, per channel	Connects to TXCTRL1 on transceiver channel primitives

Table: User Data Width Sizing Helper Block Transceiver Interface Ports (Receiver Module)
Name	Direction	Width	Clock Domain	Description
rxdata_in	Input	128 × Num. channels	RXUSRCLK2, per channel	Connects to RXDATA on transceiver channel primitives
rxctrl0_out	Input	16 × Num. channels	RXUSRCLK2, per channel	Connects to RXCTRL0 on transceiver channel primitives
rxctrl1_out	Input	16 × Num. channels	RXUSRCLK2, per channel	Connects to RXCTRL1 on transceiver channel primitives