The user data width sizing helper block simplifies the process of interfacing to the transmitter and receiver data ports of the transceiver channel primitives.
The
TXDATA
and
RXDATA
ports of each transceiver channel are 128 bits, but only those bits within the range of the configured transmitter and receiver user data widths are used; other bits are to be tied off or left unconnected, respectively. When multiple channels are enabled, it can be inconvenient to identify the active bits of the
txdata_in
and
rxdata_out
core port vectors. Furthermore, for user data widths of 20, 40, 80, or 160 bits, portions of
TXCTRL0
and
TXCTRL1
are interleaved with
TXDATA
, and portions of
RXCTRL0
and
RXCTRL1
are interleaved with
RXDATA
.
The helper block handles this transceiver-facing complexity while providing a simple user interface sized to the chosen user data width utilizing wiring only. The helper block is divided into two independent modules: a transmitter module and a receiver module. Both modules use generated HDL wire assignments. Because no combinatorial or sequential logic is used, there is no impact on the datapath.