Transmitter Module - 1.7 English

UltraScale FPGAs Transceivers Wizard LogiCORE IP Product Guide (PG182)

Document ID
PG182
Release Date
2023-05-17
Version
1.7 English

The helper block transmitter module port gtwiz_userdata_tx_in is a vector sized to the chosen transmitter user data width, multiplied by the number of enabled transceiver channels. By core convention, its least significant bits correspond to the least significant bits of the transceiver channel in the lowest enabled XY grid position.

This Figure shows the helper block configuration for an example core configuration using a 32-bit transmitter user data width and four enabled transceiver channels. With the resulting packed 128-bit gtwiz_userdata_tx_in vector, the helper block drives the appropriate bits of each transceiver channel’s TXDATA port. For 20-, 40-, 80-, and 160-bit transmitter user data widths, it also drives the appropriate bits of each transceiver channel’s TXCTRL0 and TXCTRL1 ports, handling the required de-interleaving. In other configurations, the TXCTRL0 and TXCTRL1 ports are not driven by the helper block and are available for user access.

Figure: User Data Width Sizing Helper Block (Transmitter Module) Example Configuration

Page-1 Sheet.1 Sheet.2 gtwiz_userdata_tx_in 128 (4 Channels x 32 bits) gtwiz_userdata_tx_in128 (4 Channels x 32 bits) Sheet.3 User Data Width Sizing Helper Block (Transmitter Module) User Data Width Sizing Helper Block(Transmitter Module) Standard Arrow.483 Sheet.5 Sheet.6 Standard Arrow.7 Sheet.8 Sheet.9 txdata_out 512 (4 Channels x 128 bits) txdata_out512 (4 Channels x 128 bits) Standard Arrow.10 Sheet.11 Sheet.12 txctrl0_out 64 (4 Channels x 16 bits) txctrl0_out64 (4 Channels x 16 bits) Standard Arrow.13 Sheet.14 Sheet.15 txctrl1_out 64 (4 Channels x 16 bits) txctrl1_out64 (4 Channels x 16 bits) Standard Arrow.16 Standard Arrow.17 Bracket.284 Sheet.19 To Transceiver Channel Primitives To TransceiverChannel Primitives Sheet.20 X14545 X14545