The transmitter buffer bypass controller helper block contains a user interface and a transceiver interface. The user interface provides a simple means of initiating and monitoring the status of the transceiver transmitter buffer bypass procedure. The transceiver interface implements the signaling required to control the transceiver primitive buffer bypass sequence.
Transmitter buffer bypass helper block user interface ports can be identified by the prefix gtwiz_buffbypass_tx_. For guidance on the usage of the transmitter buffer bypass controller helper block, see
Designing with the Core
.
The transmitter buffer bypass controller helper block user interface ports described in
Table: Transmitter Buffer Bypass Controller Helper Block User Interface Ports on Core (Helper Block in Core)
are present on the Wizard IP core instance when it is configured to locate the transmitter buffer bypass controller helper block in the core. The ports are also present on the helper block itself, directly accessible when the helper block is located in the example design.
In this configuration, the helper block clock port
gtwiz_buffbypass_tx_clk_in
is driven internal to the core by the same source that drives
TXUSRCLK2
of the transmitter master channel, and is not exposed.
Table: Transmitter Buffer Bypass Controller Helper Block User Interface Ports on Core (Helper Block in Core)
|
Name
|
Direction
|
Width
|
Clock Domain
|
Description
|
|
gtwiz_buffbypass_tx_reset_in
|
Input
|
1
|
gtwiz_buffbypass_tx_clk_in
|
User signal to reset the logic within the helper block. An active-High, synchronous pulse should be provided immediately after TXUSRCLK2 stabilizes for all transceiver channels.
|
|
gtwiz_buffbypass_tx_start_user_in
|
Input
|
1
|
gtwiz_buffbypass_tx_clk_in
|
Active-High user signal that is synchronously pulsed to force the transmitter buffer bypass procedure to restart. Hold Low when not used.
|
|
gtwiz_buffbypass_tx_done_out
|
Output
|
1
|
gtwiz_buffbypass_tx_clk_in
|
Active-High indicates that the transmitter buffer bypass procedure has completed.
|
|
gtwiz_buffbypass_tx_error_out
|
Output
|
1
|
gtwiz_buffbypass_tx_clk_in
|
Active-High indicates that the transmitter buffer bypass helper block encountered an error condition.
|
The transmitter buffer bypass controller helper block user interface ports described in
Table: Other Transmitter Buffer Bypass Controller Helper Block User Interface Ports (Helper Block in Example Design)
are not present on the core instance but are present on the transmitter buffer bypass controller helper block when it is included in the example design.
Table:
Other Transmitter Buffer Bypass Controller Helper Block User Interface Ports (Helper Block in Example Design)
|
Name
|
Direction
|
Width
|
Clock Domain
|
Description
|
|
gtwiz_buffbypass_tx_clk_in
|
Input
|
1
|
|
Transceiver primitive-based clock used to control the transmitter buffer bypass controller helper block. Must be driven by the same source that drives TXUSRCLK2 of the transmitter master channel.
|
|
gtwiz_buffbypass_tx_resetdone_in
|
Input
|
1
|
Async
|
Active-High indicates that the transmitter reset sequence has been completed, which allows the buffer bypass procedure to begin.
|
The transmitter buffer bypass controller helper block transceiver interface ports (described in
Table: Transmitter Buffer Bypass Controller Helper Block Transceiver Interface Port
) connect the transmitter buffer bypass controller helper block to transceiver primitives. When the helper block is located within the core, these connections are internal, and the transceiver primitive inputs that are driven by helper block outputs cannot be enabled as optional ports on the core instance. Inversely, when the helper block is located in the example design, the connections cross the core boundary, and the transceiver primitive ports that connect to the helper block are enabled by necessity.
To implement the multi-lane buffer bypass procedure, the port width of each signal scales with the number of transceiver channels that the transmitter buffer bypass controller helper block interfaces to.
Table: Transmitter Buffer Bypass Controller Helper Block Transceiver Interface Port
|
Name
|
Direction
|
Width
|
Clock Domain
|
Description
|
|
txphaligndone_in
|
Input
|
1 × Num. channels
|
Async
|
Connects to TXPHALIGNDONE of transceiver channel primitives
|
|
txphinitdone_in
|
Input
|
1 × Num. channels
|
Async
|
Connects to TXPHINITDONE of transceiver channel primitives
|
|
txdlysresetdone_in
|
Input
|
1 × Num. channels
|
Async
|
Connects to TXDLYSRESETDONE of transceiver channel primitives
|
|
txsyncout_in
|
Input
|
1 × Num. channels
|
Async
|
Connects to TXSYNCOUT of transceiver channel primitives
|
|
txsyncdone_in
|
Input
|
1 × Num. channels
|
Async
|
Connects to TXSYNCDONE of transceiver channel primitives
|
|
txphdlyreset_out
|
Output
|
1 × Num. channels
|
Tied off
|
Connects to TXPHDLYRESET of transceiver channel primitives
|
|
txphalign_out
|
Output
|
1 × Num. channels
|
Tied off
|
Connects to TXPHALIGN of transceiver channel primitives
|
|
txphalignen_out
|
Output
|
1 × Num. channels
|
Tied off
|
Connects to TXPHALIGNEN of transceiver channel primitives
|
|
txphdlypd_out
|
Output
|
1 × Num. channels
|
Tied off
|
Connects to TXPHDLYPD of transceiver channel primitives
|
|
txphinit_out
|
Output
|
1 × Num. channels
|
Tied off
|
Connects to TXPHINIT of transceiver channel primitives
|
|
txphovrden_out
|
Output
|
1 × Num. channels
|
Tied off
|
Connects to TXPHOVRDEN of transceiver channel primitives
|
|
txdlysreset_out
|
Output
|
1 × Num. channels
|
gtwiz_buffbypass_tx_clk_in (used asynchronously)
|
Connects to TXDLYSRESET of transceiver channel primitives
|
|
txdlybypass_out
|
Output
|
1 × Num. channels
|
Tied off
|
Connects to TXDLYBYPASS of transceiver channel primitives
|
|
txdlyen_out
|
Output
|
1 × Num. channels
|
Tied off
|
Connects to TXDLYEN of transceiver channel primitives
|
|
txdlyovrden_out
|
Output
|
1 × Num. channels
|
Tied off
|
Connects to TXDLYOVRDEN of transceiver channel primitives
|
|
txphdlytstclk_out
|
Output
|
1 × Num. channels
|
Tied off
|
Connects to TXPHDLYTSTCLK of transceiver channel primitives
|
|
txdlyhold_out
|
Output
|
1 × Num. channels
|
Tied off
|
Connects to TXDLYHOLD of transceiver channel primitives
|
|
txdlyupdown_out
|
Output
|
1 × Num. channels
|
Tied off
|
Connects to TXDLYUPDOWN of transceiver channel primitives
|
|
txsyncmode_out
|
Output
|
1 × Num. channels
|
Tied off
|
Connects to TXSYNCMODE of transceiver channel primitives
|
|
txsyncallin_out
|
Output
|
1 × Num. channels
|
Async
|
Connects to TXSYNCALLIN of transceiver channel primitives
|
|
txsyncin_out
|
Output
|
1 × Num. channels
|
Async
|
Connects to TXSYNCIN of transceiver channel primitives
|