The transmitter buffer bypass controller helper block automates the buffer bypass procedure that must be performed when the serial transceiver transmitter buffer is not used. The helper block implements the auto-mode buffer bypass sequence.
A single instance of the helper block is delivered with each instance of the Wizard IP core that is configured to bypass the transmitter buffer. Its user interface provides you with a simple means of initiating and monitoring the status of the transmitter buffer bypass procedure. Its transceiver interface connects to each transceiver channel primitive within the core.
For core configurations that contain multiple serial transceiver primitives, the helper block implements the multi-lane buffer bypass procedure. The transmitter master channel is specified during IP customization.
The helper block is synchronously reset when the
gtwiz_buffbypass_tx_reset_in
user input is asserted. This signal should be released as soon as
TXUSRCLK2
is stable, and before the transmitter datapath reset sequence completes for all channels. By default, the reset helper block
gtwiz_reset_tx_done_out
output is wired to the transmitter buffer bypass controller helper block
gtwiz_buffbypass_tx_resetdone_in
input. A rising edge on this port automatically initiates the transmitter buffer bypass procedure.
When the transmitter buffer bypass procedure completes, the
gtwiz_buffbypass_tx_done_out
user indicator is asserted and the
gtwiz_buffbypass_tx_error_out
indicator is set. The two user interface outputs should be considered together to decode the result of the buffer bypass procedure, as shown in
Table: Transmitter Buffer Bypass Controller Helper Block Completion Result Encoding
.
By pulsing the
gtwiz_buffbypass_tx_start_user_in
user input, you can also force the transmitter buffer bypass controller helper block to initiate the buffer bypass procedure at any time after the helper block has been reset and the initial procedure has completed.
The helper block can be located either within the core or in the example design per user selection. Depending on its location and the location of other helper blocks, the relevant ports are enabled on the core interface so that the necessary signals can cross the core boundary. If you choose to locate the helper block within the core but also wish to observe individual transceiver primitive buffer bypass status signals, you can enable the relevant ports on the core instance through the optional ports interface during IP customization.
See Product Specification , for a description of all transmitter buffer bypass controller helper block ports. See the UltraScale Architecture GTH Transceivers User Guide (UG576) [Ref 1] or UltraScale Architecture GTY Transceivers User Guide (UG578) [Ref 2] for complete information about bypassing the transmitter buffer in transceiver primitives.