Transceiver Common Primitive - 1.7 English

UltraScale FPGAs Transceivers Wizard LogiCORE IP Product Guide (PG182)

Document ID
PG182
Release Date
2023-05-17
Version
1.7 English

The transceiver common primitive is required and instantiated for core configurations where QPLL0 or QPLL1 clocking resources are used. Although it is a transceiver primitive, its logical location can be specified during IP customization. Like a helper block, it can be located either within the core or in the example design.

By providing this flexibility, it might be possible to share a single transceiver common between multiple Wizard IP core instances when the following conditions are met:

You attempt to place the physical transceiver resources of those core instances into a single transceiver Quad, and

The transceiver common configuration is identical or otherwise safe to share between the two core instances.


Transceiver common sharing between core instances is an advanced use mode and should only be performed when restrictions and limitations are fully understood. See the UltraScale Architecture GTH Transceivers User Guide (UG576) [Ref 1] or UltraScale Architecture GTY Transceivers User Guide (UG578) [Ref 2] for details on the use of the transceiver common primitive.

This Figure illustrates the case where one or more transceiver common primitives are enabled and located within the core instance, when user-specified. In this case, the QPLL#OUTCLK and QPLL#OUTREFCLK ports of the transceiver common primitives internally drive the QPLL#CLK and QPLL#REFCLK ports of the associated transceiver channel primitives, as required (where # is 0 or 1 for QPLL0 or QPLL1 , respectively). However, those same signals are also provided as outputs on the core interface as qpll#outclk_out and qpll#outrefclk_out .

Figure: Transceiver Common Located in the Core

Page-1 Sheet.1 Sheet.2 Sheet.3 Transceiver COMMON Wrapper TransceiverCOMMON Wrapper Sheet.4 Sheet.5 Sheet.6 COMMON Primitive COMMON Primitive Sheet.7 Sheet.8 Sheet.9 Transceiver CHANNEL Wrapper TransceiverCHANNEL Wrapper Sheet.10 Sheet.11 Sheet.12 CHANNEL Primitive CHANNEL Primitive Sheet.13 Wizard IP Core Wizard IP Core Standard Arrow.10 Standard Arrow.15 Sheet.16 Sheet.17 Sheet.18 qpll#outclk_out qpll#outclk_out Sheet.19 qpll#outrefclk_out qpll#outrefclk_out Connector Dot.387 Connector Dot.21 Sheet.22 X14547 X14547

This Figure illustrates the case where one or more transceiver common primitives are enabled but located within the example design when user-specified. In this case, the QPLL#OUTCLK and QPLL#OUTREFCLK ports of the transceiver common primitives drive the qpll#clk_in and qpll#refclk_in input ports on the core interface, which in turn are connected to the QPLL#CLK and QPLL#REFCLK ports of the associated transceiver channel primitives.

Figure: Transceiver Common Located in the Example Design

Page-1 Sheet.1 Sheet.2 Sheet.3 Transceiver COMMON Wrapper TransceiverCOMMON Wrapper Sheet.4 Sheet.5 Sheet.6 COMMON Primitive COMMON Primitive Sheet.7 Sheet.8 Sheet.9 Transceiver CHANNEL Wrapper TransceiverCHANNEL Wrapper Sheet.10 Sheet.11 Sheet.12 CHANNEL Primitive CHANNEL Primitive Sheet.13 Wizard IP Core Wizard IP Core Standard Arrow.10 Standard Arrow.15 Sheet.16 qpll#clk_in qpll#clk_in Sheet.17 qpll#refclk_in qpll#refclk_in Sheet.18 X14548 X14548 Sheet.19 IP Example Design IP Example Design Sheet.20 qpll#outclk_int qpll#outclk_int Sheet.21 qpll#outrefclk_int qpll#outrefclk_int

When integrating multiple core instances into your system, the two types of customizations described earlier can be combined to share the transceiver common resources that are present within the instance that contains them. This Figure illustrates how the output ports on the core instance that contains the transceiver common resources can be easily connected to the associated input ports on the core instance which does not. Essentially, the two instances are connected when integrating the cores, excluding the example design wrappers.

Figure: Transceiver Common Sharing

Page-1 Sheet.1 Sheet.2 Sheet.3 Transceiver CHANNEL Wrapper TransceiverCHANNEL Wrapper Sheet.4 Sheet.5 Sheet.6 CHANNEL Primitive CHANNEL Primitive Sheet.7 Wizard IP Core Wizard IP Core Sheet.8 Sheet.9 Sheet.10 Transceiver COMMON Wrapper TransceiverCOMMON Wrapper Sheet.11 Sheet.12 Sheet.13 COMMON Primitive COMMON Primitive Sheet.14 Sheet.15 Sheet.16 Transceiver CHANNEL Wrapper TransceiverCHANNEL Wrapper Sheet.17 Sheet.18 Sheet.19 CHANNEL Primitive CHANNEL Primitive Sheet.20 Wizard IP Core Wizard IP Core Standard Arrow.10 Standard Arrow.15 Sheet.23 Sheet.24 Sheet.25 qpll#outclk_out qpll#outclk_out Sheet.26 qpll#outrefclk_out qpll#outrefclk_out Connector Dot.387 Connector Dot.21 Sheet.29 X14549 X14549 Sheet.30 Sheet.31 Sheet.32 qpll#clk_in qpll#clk_in Sheet.33 qpll#refclk_in qpll#refclk_in

See AR#65228 for information on how to share a COMMON block using GTH transceivers.