Synthesis and Implementation - 1.7 English

UltraScale FPGAs Transceivers Wizard LogiCORE IP Product Guide (PG182)

Document ID
PG182
Release Date
2023-05-17
Version
1.7 English

The wizard example design can be synthesized and implemented to quickly demonstrate core and transceiver functionality in hardware. For more information, see Example Design .

For details about synthesis and implementation, see the Vivado Design Suite User Guide: Designing with IP (UG896) [Ref 8] .