In GTH transceiver configurations targeting engineering sample (ES1 or ES2) UltraScale devices where the CPLL is used as either the transmitter PLL type, receiver PLL type, or the source of a selectable TXOUTCLK frequency, a special CPLL calibration procedure runs as part of the PLL reset sequence. GTH transceiver core configurations that target engineering sample (ES1 or ES2) UltraScale devices and that use the CPLL have these additional reset requirements and characteristics:
• Do not attempt to perform transceiver channel DRP transactions in the time period between initializing a CPLL reset and assertion of the CPLL lock indicator, or in the time period between releasing the CPLL from power-down mode and initializing a CPLL reset. During these times, transceiver channel DRP transactions are ignored.
•
Do not attempt to assert
txprogdivreset_in
or change the value of the
txoutclksel_in
port in the time period between initializing a CPLL reset and assertion of the CPLL lock indicator, or in the time period between releasing the CPLL from power-down mode and initializing a CPLL reset. During this time, inputs on these ports are ignored.
•
Each bit of the
drpclk_in
port must be driven by the free-running clock, operating at exactly the frequency specified during IP customization. See
Performance
, for more details.
•
If the transmitter user clocking network helper block is located in the example design, then the
gtwiz_userclk_tx_reset_in
port on the helper block and the
gtwiz_userclk_tx_reset_in
port on the core must be driven by the same source. See
Transmitter User Clocking Network Helper Block Ports
, for more details.
• The time required to achieve CPLL lock in hardware operation can vary between CPLL resets.
•
Resetting the CPLL temporarily disrupts the
TXOUTCLK
signal, and therefore also the clocks produced by the transmitter user clocking network helper block, even when the CPLL is used exclusively for the receiver data path. This is because the CPLL calibration procedure takes control of
TXOUTCLK
during CPLL reset, irrespective of which resources the CPLL drives. If runtime disruption to transmitter user clocks is not tolerable in configurations where the CPLL drives only receiver resources, take care to reset and achieve lock on the CPLL prior to, or separate from bringing up transmitter resources.
Initialization of a CPLL reset can include pulses of
gtwiz_reset_all_in
,
gtwiz_reset_tx_pll_and_datapath_in
(when the CPLL is used for the transmitter datapath),
gtwiz_reset_rx_pll_and_datapath_in
(when the CPLL is used for the receiver datapath), or
cpllreset_in
(when the reset controller helper block is not used).
CPLL lock indicators can include
gtwiz_reset_tx_done_out
(when the CPLL is used for the transmitter data path),
gtwiz_reset_rx_done_out
(when the CPLL is used for the receiver datapath), or
cplllock_out
(when the reset controller helper block is not used, or if a direct CPLL lock indicator is desired).