The following table shows the revision history for this document.
|
Date |
Version |
Revision |
|---|---|---|
|
05/17/2023 |
1.7 |
• Added additional information in Transmitter frame Basic Tab section. • Added additional information in Optional Port Enablement Interface Optional Features Tab section. |
|
12/04/2020 |
1.7 |
• Updated Table 3-1. |
|
10/30/2019 |
1.7 |
• Updated Enabling CPLL Calibration block for UltraScale+ Devices section. • Updated USER_GTPOWERGOOD_DELAY_EN parameter value. |
|
06/21/2019 |
1.7 |
• Updated description for USER_GTPOWERGOOD_DELAY_EN |
|
04/04/2018 |
1.7 |
• Updated descriptions of gtgrefclk0_in, gtgrefclk1_in, and gtgrefclk_in. • Updated descriptions of rxpllclksel_in and txpllclksel_in • Reference to Xilinx Answer added in Enabling CPLL Calibration block for UltraScale+ devices section • Note about the usage of DISABLE_LOC_XDC added under Required Constraints in Design Flow Steps chapter |
|
10/04/2017 |
1.7 |
• Updated description and guidance for usage of SIM_CPLL_CAL_BYPASS |
|
06/07/2017 |
1.7 |
• Updated core to v1.7 • CPLL Calibration block is enabled by default for CPLL configurations of GTHE4 and GTYE4 • gtpowergood_out is added as a mandatory port |
|
04/05/2017 |
1.6 |
• Updated Simulation guidance for CPLL Calibration block • Updated Spread Spectrum related guidance |
|
11/30/2016 |
1.6 |
• Updated for CPLL Calibration block for UltraScale+ devices |
|
10/05/2016 |
1.6 |
• Updated for 2016.3 release • Added In-System IBERT Core instantiation in Example design with 2016.3 • Added reference to PG246 - In-System IBERT LogiCORE IP Product Guide |
|
11/18/2015 |
1.6 |
• Added support for UltraScale+ ™ families |
|
09/30/2015 |
1.6 |
• Updated the maximum frequency in the Free-Running Clock Maximum Frequency table • Updated the resource utilization data • Clarified that the reset controller helper block's reset all input is falling-edge triggered • Wizard options: ° Added QPLL Fractional-N ° Removed Fractional part of QPLL feedback divider (Advanced option) ° Updated descriptions for Enabling a channel (Physical Resources tab) |
|
02/23/2015 |
1.5 |
• Updated for the core v1.5 • Specified engineering sample (ES1 or ES2) devices in all references to GTH transceiver configurations which use the CPLL • Added Virtual Input/Output (VIO) core instance to the example design • In Chapter 4, clarified that the core is not available in Vivado IP integrator, and further clarified the constraints support details |
|
10/01/2014 |
1.4 |
• Updated for 2014.3 release • IP Facts: Updated eighth bullet in Features • Chapter 1, updated ninth bullet in Feature Summary • Chapter 2: ° Updated number of LUTs and flip-flops in Resource Utilization, including Table 2-2 ° In Table 2-3, removed gtwiz_reset_rx_data_good_in and updated description of gtwiz_reset_rx_cdr_stable_out ° Added gtpowergood_in to Table 2-6 • Chapter 3: Updated second paragraph in Reset Sequencing and Other Services • Chapter 4: ° Updated Enabling a channel bullet in Channel Table and Channel Graphic ° Updated Figure 4-1 to Figure 4-4 • Chapter 5: ° Added second bullet to Core-level Constraints ° In Clock Frequencies, replaced create_clock commands with set_case_analysis commands ° Updated placeholder package pin constraints in I/O Standard and Placement ° Updated XDC file commands in Other Constraints ° Updated first bullet and last paragraph in Purpose of the Example Design ° Updated Hierarchy and Structure ° In Figure 5-1, added Initialization block and renamed PRBS Lock I/O block to Link Status ° In Table 5-1, added rxrecclkout_ch<j>_p/n and updated link_down_latched_reset_in, link_status_out, and link_down_latched_out ports ° Added Link Status and Initialization ° Removed third bullet in Limitations of the Example Design • Chapter 6: ° Updated second and third paragraphs in Simulating the Example Design ° Updated Simulation Behavior, including Figure 6-1 • Appendix B: Updated ILA and VIO versions in Vivado Lab Edition |
|
06/04/2014 |
1.3 |
Updated for 2014.2 release • Corrected titles for UltraScale FPGAs GTH Transceivers User Guide (UG576) and UltraScale FPGAs GTY Transceivers User Guide (UG578) throughout • Chapter 2: ° In Table 2-2, updated reset controller, transmitter buffer bypass controller utilization, and receiver buffer bypass controller numbers ° Added a row for user data width sizing ° In Table 2-3, updated description of gtwiz_reset_rx_data_good_in • Chapter 3: ° Added recovered clock buffers to Designing with the Example Design ° Updated first paragraph of Reset Controller Helper Block ° Updated receiver reset state machine in Figure 3-1 ° Updated third paragraph of Reset Sequencing and Other Services • Chapter 4: ° Updated first bullet in System Frame ° Updated Encoding bullet in Transmitter Frame ° Updated decoding bullet in Receiver Frame ° Updated first paragraph in Channel Table and Channel Graphic ° Updated fourth bullet in Helper Block Location Frame ° Updated Figure 4-1 to Figure 4-4 • Chapter 5: ° Removed core-level clock period constraints bullet from Core-level Constraints ° Updated Out-of-Context Constraints ° Updated Clock Frequencies ° Chapter 5: Updated last paragraph of Adapting the Example Design • Chapter 6: Updated Figure 6-1 |
|
04/02/2014 |
1.2 |
Updated for 2014.1 release • Chapter 1: Updated fifth bullet in Feature Summary • Chapter 2: ° Updated note in Maximum Frequencies ° In Table 2-3, added gtwiz_reset_qpll0lock_in, gtwiz_reset_qpll1lock_in, gtwiz_reset_qpll0reset_out, and gtwiz_reset_qpll1reset_out ports ° Updated description of gtwiz_reset_rx_cdr_stable_out port ° Added gtwiz_userclk_tx_reset_in port to Table 2-9 ° In Table 2-25, corrected rxckokreset_in and rxckokdone_out to rxckcalreset_in and rxckcaldone_out, respectively • Chapter 3: ° Updated paragraphs after Figure 3-1 ° Added Special GTH Transceiver CPLL Reset Requirements for Engineering Sample (ES1 or ES2) Devices ° Updated description of CDR stability in second paragraph of Reset Sequencing and Other Services • Chapter 4: ° Updated all figures ° Added “Fractional part of QPLL feedback divider” to Transmitter Frame (Advanced Section) ° In Receiver Frame (Advanced Section), added Fractional part of QPLL feedback divider and Enable Out of Band signaling (OOB)/Electrical Idle and removed Jitter tolerance mask: Mask corner frequency (MHz) and Jitter tolerance mask: Mask low frequency slope (dB/decade) ° Added Free-Running and DRP Clock Frequency (MHz) ° Updated Manual alignment (RXSLIDE) mode bullet in Receiver Comma Detection and Alignment Section ° Updated Enable and select number of sequences to use bullet in Receiver Channel Bonding Section ° Updated Enable and select number of sequences to use bullet in Receiver Clock Correction Section ° Added Advanced Clocking Section and SATA Section ° Removed note from Include reset controller in the... bullet in Helper Block Location Frame • Chapter 5: ° Updated first bullet in Core-level Constraints ° Updated Clock Frequencies • Appendix C: Added UltraScale FPGAs GTY Transceivers User Guide (UG578) and Virtex UltraScale Architecture Data Sheet: DC and AC Switching Characteristics (DS893) to References |
|
12/18/2013 |
1.1 |
Initial Xilinx release |