The basic Wizard HDL is highly structural and uses a negligible amount of device resources to instantiate and wire the transceiver primitives for use. In GTH transceiver configurations targeting engineering sample (ES1 or ES2) UltraScale devices where the CPLL is used as either the transmitter PLL type, receiver PLL type, or as the source of a selectable TXOUTCLK frequency, CPLL calibration logic is included. One BUFG_GT and approximately 280 LUTs and 285 flip-flops are utilized per enabled transceiver channel in these configurations.
The device utilization of the optional helper blocks is shown in Table: Resource Utilization of Helper Blocks . These resources are only consumed when the relevant helper block is enabled and used within the core, or otherwise included in your design. Resources are shown per helper block instance, although most configurations that enable a helper block use only one instance.
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Device Resources
|
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|---|---|---|---|---|
|
Type |
Configuration |
LUTs |
Flip-Flops |
Clock Buffers |
|
Reset controller |
Any |
120 |
195 |
0 (1) |
|
Transmitter user clocking network |
F TXUSRCLK = F TXUSRCLK2 |
0 |
2 |
1 (BUFG_GT) |
|
F TXUSRCLK ≠ F TXUSRCLK2 |
0 |
2 |
2 (BUFG_GT) |
|
|
Receiver user clocking network |
F RXUSRCLK = F RXUSRCLK2 |
0 |
2 |
1 (BUFG_GT) |
|
F RXUSRCLK ≠ F RXUSRCLK2 |
0 |
2 |
2 (BUFG_GT) |
|
|
Transmitter buffer bypass controller |
Single-lane |
8 |
25 |
0 |
|
Multi-lane |
<20 |
25 |
0 |
|
|
Receiver buffer bypass controller |
Single-lane |
8 |
25 |
0 |
|
Multi-lane |
<20 |
25 |
0 |
|
|
User data width sizing |
Any |
0 |
0 |
0 |
|
Notes:
1. A shareable BUFG for the free-running clock is not included in the helper block HDL. |
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Resources required are derived from post-synthesis reports and may change during implementation.