Reset Sequencing and Other Services - 1.7 English

The transmitter and receiver reset state machines implement the relevant reset sequences as specified in the UltraScale Architecture GTH Transceivers User Guide (UG576) [Ref 1] or UltraScale Architecture GTY Transceivers User Guide (UG578) [Ref 2] . The reset controller helper block transceiver interface connects to the transceiver primitives. To implement proper TXUSERRDY and RXUSERRDY signaling, wiring exists between the reset controller helper block and both transmitter and receiver user clocking network helper blocks. Also, if the transmitter or receiver buffers are bypassed, wiring exists between the reset helper block and the relevant buffer bypass controller helper blocks to initiate the buffer bypass sequences upon completion of the reset sequences. This wiring exists regardless of the location of each helper block.

Following device configuration, no reset helper block reset inputs should be asserted until transceiver power is reported as good. The reset controller helper block internally holds all PLL and datapath resources in reset until GTPOWERGOOD is High from all transceiver channels, then subsequently resets all transceiver resources by transitioning once through the reset all state machine. As a result, you should wait for either the initial assertion of all bits of the gtpowergood_out port (if you have exposed the port), or of both gtwiz_reset_tx_done_out and gtwiz_reset_rx_done_out before attempting subsequent resets of any kind.

However, with UltraScale+ devices, it has been observed that if the JTAG frequency with which the FPGA is programmed is greater than 6MHz, then there could be some initial instability on the GT Reference clock output from IBUFDS_GTE4 followed by BUFG_GT . To avoid this, a user delay powergood logic is added by default inside the GT Wizard IP to hold the gtpowergood_out so that the logic is kept in reset initially. USER_GTPOWERGOOD_DELAY_EN user parameter has been added for enabling this. It is recommended that the value of this parameter should always be 1, regardless of the actual JTAG frequency used to program.

When the transmitter reset state machine is complete, if one or more PLLs that clock transceiver primitive transmitter datapaths lose lock, the gtwiz_reset_tx_done_out user indicator is de-asserted. A reset sequence does not automatically restart in this circumstance; user intervention is required.

Similarly, when the receiver reset state machine has completed, if one or more PLLs that clock transceiver primitive receiver datapaths lose lock, the gtwiz_reset_rx_done_out user indicator is de-asserted. A reset sequence does not automatically restart in this circumstance, user intervention is required.

The helper block can be located either within the core or in the example design per user selection. Depending on its location and the location of other helper blocks, the relevant ports are enabled on the core interface so that the necessary signals can cross the core boundary.

If additional reset control or related ports are required for your application, or if you wish to observe individual transceiver primitive reset status signals, you can enable the relevant ports on the core instance using the optional ports interface during IP customization.

See Product Specification , for a description of all reset controller block ports. See the UltraScale Architecture GTH Transceivers User Guide (UG576) [Ref 1] or UltraScale Architecture GTY Transceivers User Guide (UG578) [Ref 2] for complete documentation on resetting and initializing the transceiver primitives.