Reset Controller Helper Block Ports

The reset controller helper block contains a user interface and a transceiver interface. The user interface provides a simple means of initiating and monitoring the completion of transceiver reset procedures. The transceiver interface implements the signaling required to control the various transceiver primitive reset sequences.

Reset controller helper block user interface ports can be identified by the prefix gtwiz_reset_. For guidance on the usage of the reset controller helper block, see Designing with the Core .

The reset controller helper block user interface ports described in Table: Reset Controller Helper Block User Interface Ports on Core (Helper Block in Core) are present on the Wizard IP core instance when it is configured to locate the reset controller helper block in the core. They are also present on the helper block itself, directly accessible when the helper block is located in the example design.

Table: Reset Controller Helper Block User Interface Ports on Core (Helper Block in Core)
Name	Direction	Width	Clock Domain	Description
gtwiz_reset_clk_freerun_in	Input	1		Free-running clock used to reset transceiver primitives. Must be toggling prior to device configuration. See Performance for maximum frequency guidance.
gtwiz_reset_all_in	Input	1	Async	User signal to reset the phase-locked loops (PLLs) and active data directions of transceiver primitives. The falling edge of an active-High, asynchronous pulse of at least one gtwiz_reset_clk_freerun_in period in duration initializes the process.
gtwiz_reset_tx_pll_and_datapath_in	Input	1	Async	User signal to reset the transmit data direction and associated PLLs of transceiver primitives. An active-High, asynchronous pulse of at least one gtwiz_reset_clk_freerun_in period in duration initializes the process.
gtwiz_reset_tx_datapath_in	Input	1	Async	User signal to reset the transmit data direction of transceiver primitives. An active-High, asynchronous pulse of at least one gtwiz_reset_clk_freerun_in period in duration initializes the process.
gtwiz_reset_rx_pll_and_datapath_in	Input	1	Async	User signal to reset the receive data direction and associated PLLs of transceiver primitives. An active-High, asynchronous pulse of at least one gtwiz_reset_clk_freerun_in period in duration initializes the process.
gtwiz_reset_rx_datapath_in	Input	1	Async	User signal to reset the receive data direction of transceiver primitives. An active-High, asynchronous pulse of at least one gtwiz_reset_clk_freerun_in period in duration initializes the process.
gtwiz_reset_rx_cdr_stable_out	Output	1	gtwiz_reset_clk_ freerun_in	Active-High indication that the clock and data recovery (CDR) circuits of the transceiver primitives are stable. Reserved; do not use.
gtwiz_reset_qpll0lock_in	Input	1 × Num. commons	Async	QPLL0 lock signal, present when the transceiver common is located in the example design and QPLL0 is used as either the transmitter or receiver PLL type.
gtwiz_reset_qpll1lock_in	Input	1 × Num. commons	Async	QPLL1 lock signal, present when the transceiver common is located in the example design and QPLL1 is used as either the transmitter or receiver PLL type.
gtwiz_reset_tx_done_out	Output	1	TXUSRCLK2 of TX master channel	Active-High indication that the transmitter reset sequence of transceiver primitives as initiated by the reset controller helper block has been completed.
gtwiz_reset_rx_done_out	Output	1	RXUSRCLK2 of RX master channel	Active-High indication that the receiver reset sequence of transceiver primitives as initiated by the reset controller helper block has been completed.
gtwiz_reset_qpll0reset_out	Output	1 × Num. commons	gtwiz_reset_clk_ freerun_in	QPLL0 reset signal, present when the transceiver common is located in the example design and QPLL0 is used as either the transmitter or receiver PLL type.
gtwiz_reset_qpll1reset_out	Output	1 × Num. commons	gtwiz_reset_clk_ freerun_in	QPLL1 reset signal, present when the transceiver common is located in the example design and QPLL1 is used as either the transmitter or receiver PLL type.

The reset controller helper block user interface ports described in Table: Reset Controller Helper Block User Interface Ports on Core (Helper Block in Example Design) are present on the core instance when it is configured to locate the reset controller helper block in the example design.

Table: Reset Controller Helper Block User Interface Ports on Core (Helper Block in Example Design)
Name	Direction	Width	Clock Domain	Description
gtwiz_reset_tx_done_in	Input	1	Async	Upon successful completion of the transmitter reset sequence, this active-High port must be asserted to allow dependent helper blocks within the core to operate. The reset controller helper block drives this port by default.
gtwiz_reset_rx_done_in	Input	1	Async	Upon successful completion of the receiver reset sequence, this active-High port must be asserted to allow dependent helper blocks within the core to operate. The reset controller helper block drives this port by default.

The reset controller helper block user interface ports described in Table: Other Reset Controller Helper Block User Interface Ports (Helper Block in Example Design) are not present on the core instance. However, these ports appear on the reset controller helper block itself when it is included in the example design.

Table: Other Reset Controller Helper Block User Interface Ports (Helper Block in Example Design)
Name	Direction	Width	Clock Domain	Description
gtwiz_reset_userclk_tx_active_in	Input	1	Async	When the TXUSRCLK and TXUSRCLK2 signals that drive transceiver primitives are active and stable, this active-High port must be asserted for the transmitter reset sequence to complete. The transmitter user clocking network helper block drives this port by default.
gtwiz_reset_userclk_rx_active_in	Input	1	Async	When the RXUSRCLK and RXUSRCLK2 signals that drive transceiver primitives are active and stable, this active-High port must be asserted to allow the receiver reset sequence to complete. The receiver user clocking network helper block drives this port by default.

The reset controller helper block transceiver interface ports described in Table: Reset Controller Helper Block Transceiver Interface Ports connect the reset controller helper block to transceiver primitives. When the helper block is located within the core, these connections are internal and the transceiver primitive inputs that are driven by helper block outputs cannot be enabled as optional ports on the core instance. Inversely, when the helper block is located in the example design, the connections cross the core boundary so the transceiver primitive ports that connect to the helper block are enabled by necessity.

Table: Reset Controller Helper Block Transceiver Interface Ports
Name	Direction	Width	Clock Domain	Description
gtpowergood_in	Input	1	Async	Logical AND of all GTPOWERGOOD signals produced by transceiver channel logic.
txusrclk2_in	Input	1		TXUSRCLK2 of master transceiver channel.
plllock_tx_in	Input	1	Async	Logical AND of all lock signals produced by PLLs that clock the transmit datapath of transceiver channel primitives.
txresetdone_in	Input	1	Async	Logical AND of all TXRESETDONE signals produced by transceiver channel primitives.
rxusrclk2_in	Input	1		RXUSRCLK2 of master transceiver channel.
plllock_rx_in	Input	1	Async	Logical AND of all lock signals produced by PLLs that clock the receive datapath of transceiver channel primitives.
rxcdrlock_in	Input	1	Async	Logical AND of all RXCDRLOCK signals produced by transceiver channel primitives.
rxresetdone_in	Input	1	Async	Logical AND of all RXRESETDONE signals produced by transceiver channel primitives.
pllreset_tx_out	Output	1	gtwiz_reset_clk_freerun_in (used asynchronously)	Active-High signal fanned out to the reset ports of all PLLs that clock the transmit datapath of transceiver channel primitives.
txprogdivreset_out	Output	1	gtwiz_reset_clk_freerun_in (used asynchronously)	Active-High signal fanned out to TXPROGDIVRESET port of all transceiver channel primitives.
gttxreset_out	Output	1	gtwiz_reset_clk_freerun_in (used asynchronously)	Active-High signal fanned out to GTTXRESET port of all transceiver channel primitives.
txuserrdy_out	Output	1	gtwiz_reset_clk_freerun_in (used asynchronously)	Active-High signal fanned out to TXUSERRDY port of all transceiver channel primitives.
pllreset_rx_out	Output	1	gtwiz_reset_clk_freerun_in (used asynchronously)	Active-High signal fanned out to the reset ports of all PLLs that clock the receive datapath of transceiver channel primitives.
rxprogdivreset_out	Output	1	gtwiz_reset_clk_freerun_in (used asynchronously)	Active-High signal fanned out to RXPROGDIVRESET port of all transceiver channel primitives.
gtrxreset_out	Output	1	gtwiz_reset_clk_freerun_in (used asynchronously)	Active-High signal fanned out to GTRXRESET port of all transceiver channel primitives.
rxuserrdy_out	Output	1	gtwiz_reset_clk_freerun_in (used asynchronously)	Active-High signal fanned out to RXUSERRDY port of all transceiver channel primitives.

Note: All input/output ports which are described as async, are synchronized to gtwiz_reset_clk_freerun_in in the example design. In user designs, all asynchronous signals coming as inputs to the IP, should be asserted for sufficient time. This ensures that the synchronizers present inside the IP sampling on the gtwiz_reset_clk_freerun_in identify the toggles on these ports.

The reset controller helper block ports described in Table: Reset Controller Helper Block Tie-off Ports must be tied off. By default, appropriate tie-offs are provided for each core customization.

Table: Reset Controller Helper Block Tie-off Ports
Name	Direction	Width	Clock Domain	Description
tx_enabled_tie_in	Input	1	gtwiz_reset_clk_freerun_in	When tied High, transmitter resources are reset as part of the sequence in response to gtwiz_reset_all_in.
rx_enabled_tie_in	Input	1	gtwiz_reset_clk_freerun_in	When tied High, receiver resources are reset as part of the sequence in response to gtwiz_reset_all_in.
shared_pll_tie_in	Input	1	gtwiz_reset_clk_freerun_in	When tied High, the shared PLL is reset only once as part of the sequence in response to gtwiz_reset_all_in.

Reset Controller Helper Block Ports - 1.7 English

UltraScale FPGAs Transceivers Wizard LogiCORE IP Product Guide (PG182)