The receiver user clocking network helper block provides a single interface with a source clock input port driven by a transceiver primitive-based output clock. Receiver user clocking network helper block ports can be identified by the prefix gtwiz_userclk_rx_. For guidance on the usage of the receiver user clocking network helper block, see
Designing with the Core
.
The receiver user clocking network helper block ports described in
Table: Receiver User Clocking Network Helper Block Ports on Core (Helper Block in Core)
are present on the wizard core instance, when it is configured to locate the receiver user clocking network helper block in the core.
Table:
Receiver User Clocking Network Helper Block Ports on Core (Helper Block in Core)
|
Name
|
Direction
|
Width
|
Clock Domain
|
Description
|
|
gtwiz_userclk_rx_reset_in
|
Input
|
1
|
Async
|
User signal to reset the clocking resources within the helper block. The active-High assertion should remain until gtwiz_userclk_rx_srcclk_in/out is stable.
|
|
gtwiz_userclk_rx_srcclk_out
|
Output
|
1
|
|
Transceiver primitive-based clock source used to derive and buffer the RXUSRCLK and RXUSRCLK2 outputs.
|
|
gtwiz_userclk_rx_usrclk_out
|
Output
|
1
|
|
Drives RXUSRCLK of transceiver channel primitives. Derived from gtwiz_userclk_rx_srcclk_in/out, buffered and divided as necessary by BUFG_GT primitive.
|
|
gtwiz_userclk_rx_usrclk2_out
|
Output
|
1
|
|
Drives RXUSRCLK2 of transceiver channel primitives. Derived from gtwiz_userclk_rx_srcclk_in/out, buffered and divided as necessary by BUFG_GT primitive if required.
|
|
gtwiz_userclk_rx_active_out
|
Output
|
1
|
gtwiz_userclk_rx_usrclk2_out
|
Active-High indication that the clocking resources within the helper block are not held in reset.
|
The receiver user clocking network helper block ports described in
Table: Receiver User Clocking Network Helper Block User Interface Ports on Core (Helper Block in Example Design)
are present on the core instance, when it is configured to locate the receiver user clocking network helper block in the example design.
Table:
Receiver User Clocking Network Helper Block User Interface Ports on Core (Helper Block in Example Design)
|
Name
|
Direction
|
Width
|
Clock Domain
|
Description
|
|
gtwiz_userclk_rx_active_in
|
Input
|
1
|
Async
|
When the clocks produced by the receiver user clocking network helper block are active, this active-High port must be asserted to allow dependent helper blocks within the core to operate. The receiver user clocking network helper block drives this port by default.
|
The receiver user clocking network helper block ports described in
Table: Other Receiver User Clocking Network Helper Block User Interface Ports (Helper Block in Example Design)
are not present on the core instance, but are present on the receiver user clocking network helper block itself when it is included in the example design.
Table:
Other Receiver User Clocking Network Helper Block User Interface Ports (Helper Block in Example Design)
|
Name
|
Direction
|
Width
|
Clock Domain
|
Description
|
|
gtwiz_userclk_rx_srcclk_in
|
Input
|
1
|
|
Transceiver primitive-based clock source used to derive and buffer RXUSRCLK and RXUSRCLK2 outputs.
|