Receiver User Clocking Network Helper Block - 1.7 English

UltraScale FPGAs Transceivers Wizard LogiCORE IP Product Guide (PG182)
Document ID
PG182
Release Date
2023-05-17
Version
1.7 English

The receiver user clocking network helper block is a simple module used to derive and buffer the appropriate clocks to drive RXUSRCLK and RXUSRCLK2 inputs of one or more transceiver channel primitives.

A single instance of the helper block is usually delivered with each instance of the Wizard IP core. Alternatively, when the receiver elastic buffer is bypassed and single-lane buffer bypass mode is enabled, one instance of the helper block is delivered for, and wired to, each independently clocked transceiver channel primitive instance.

By default, the helper block source clock input port gtwiz_userclk_rx_srcclk_in is driven by either the RXOUTCLK port of the master transceiver channel (in most configurations) or by the RXOUTCLK port of the corresponding transceiver channel (when single-lane buffer bypass is used). Within the helper block, this source drives either one or two BUFG_GT primitives, which are global clock buffers that are capable of clock division.


As shown in This Figure , if RXUSRCLK and RXUSRCLK2 frequencies are identical (which is the case when the receiver user data width is narrower than or equal to the size of the internal data width), then only a single BUFG_GT is instantiated within the helper block. This buffer drives both gtwiz_userclk_rx_usrclk_out and gtwiz_userclk_rx_usrclk2_out helper block output ports, which are wired to the RXUSRCLK and RXUSRCLK2 input ports, respectively, of the appropriate transceiver channel primitive(s). The helper block configures the BUFG_GT to divide the source clock down to the correct user clock frequency as required.

Figure: Receiver User Clocking Network Helper Block (with One BUFG_GT)

Page-1 Sheet.1 Sheet.2 Sheet.3 Sheet.4 Sheet.5 Sheet.6 Sheet.7 Sheet.8 Sheet.9 Sheet.10 Sheet.11 Sheet.12 Sheet.13 Sheet.14 Sheet.15 Sheet.16 Sheet.17 Sheet.18 gtwiz_userclk_rx_srcclk_in From RXOUTCLK of RX Master Channel gtwiz_userclk_rx_srcclk_inFrom RXOUTCLK of RX Master Channel Sheet.19 gtwiz_userclk_rx_usrclk_out To RXUSRCLK of All Channels gtwiz_userclk_rx_usrclk_outTo RXUSRCLK of All Channels Sheet.20 gtwiz_userclk_rx_usrclk2_out To RXUSRCLK2 of All Channels gtwiz_userclk_rx_usrclk2_outTo RXUSRCLK2 of All Channels Sheet.21 Receiver User Clocking Network Helper Block For Most Configur... Receiver User Clocking Network Helper BlockFor Most Configurations(FRXUSRCLK = FRXUSRCLK2) Sheet.22 / / Sheet.23 / / Standard Arrow.483 Standard Arrow.4 Standard Arrow.488 Sheet.27 Sheet.28 Sheet.29 Sheet.30 Sheet.31 Sheet.32 Sheet.33 Sheet.34 Sheet.35 Sheet.36 Sheet.37 Sheet.38 Sheet.39 Sheet.40 Sheet.41 Sheet.42 Sheet.43 Sheet.44 X14543 X14543 Sheet.45 gtwiz_userclk_rx_srcclk_in From RXOUTCLK of Corresponding Cha... gtwiz_userclk_rx_srcclk_inFrom RXOUTCLK of Corresponding Channel Sheet.46 gtwiz_userclk_rx_usrclk_out To RXUSRCLK of Corresponding Chan... gtwiz_userclk_rx_usrclk_outTo RXUSRCLK of Corresponding Channel Sheet.47 gtwiz_userclk_rx_usrclk2_out To RXUSRCLK2 of Corresponding Ch... gtwiz_userclk_rx_usrclk2_outTo RXUSRCLK2 of Corresponding Channel Sheet.48 Receiver User Clocking Network Helper Block For Single-Lane R... Receiver User Clocking Network Helper BlockFor Single-Lane RX Elastic Buffer Bypass Configurations(FRXUSRCLK = FRXUSRCLK2) Sheet.49 / / Sheet.50 / / Standard Arrow.38 Standard Arrow.39 Standard Arrow.40

As shown in This Figure , if RXUSRCLK is twice the frequency of RXUSRCLK2 (which is the case when the receiver user data width is wider than the internal data width), then two BUFG_GT primitives are instantiated within the helper block. The helper block configures one BUFG_GT to divide the source clock down to the correct receiver datapath frequency and drive the gtwiz_userclk_rx_usrclk_out helper block output port, which is wired to the RXUSRCLK input port of the appropriate transceiver channel primitive(s). The helper block configures the other BUFG_GT to divide the source clock down to the correct receiver user interface frequency and drive the gtwiz_userclk_rx_usrclk2_out helper block output port, which is wired to the RXUSRCLK2 input port of the appropriate transceiver channel primitive(s).

Figure: Receiver User Clocking Network Helper Block (with Two BUFG_GT Primitives)

Page-1 Sheet.1 Sheet.2 Sheet.3 Sheet.4 gtwiz_userclk_rx_srcclk_in From RXOUTCLK of RX Master Channel gtwiz_userclk_rx_srcclk_inFrom RXOUTCLK of RX Master Channel Sheet.5 gtwiz_userclk_rx_usrclk_out To RXUSRCLK of All Channels gtwiz_userclk_rx_usrclk_outTo RXUSRCLK of All Channels Sheet.6 gtwiz_userclk_rx_usrclk2_out To RXUSRCLK2 of All Channels gtwiz_userclk_rx_usrclk2_outTo RXUSRCLK2 of All Channels Sheet.7 Receiver User Clocking Network Helper Block For Most Configur... Receiver User Clocking Network Helper BlockFor Most Configurations(FRXUSRCLK <> FRXUSRCLK2) Sheet.8 / / Standard Arrow.483 Standard Arrow.4 Sheet.11 Sheet.12 Sheet.13 Sheet.14 X14544 X14544 Sheet.15 gtwiz_userclk_rx_srcclk_in From RXOUTCLK of Corresponding Cha... gtwiz_userclk_rx_srcclk_inFrom RXOUTCLK of Corresponding Channel Sheet.16 gtwiz_userclk_rx_usrclk_out To RXUSRCLK of Corresponding Chan... gtwiz_userclk_rx_usrclk_outTo RXUSRCLK of Corresponding Channel Sheet.17 gtwiz_userclk_rx_usrclk2_out To RXUSRCLK2 of Corresponding Ch... gtwiz_userclk_rx_usrclk2_outTo RXUSRCLK2 of Corresponding Channel Sheet.18 Receiver User Clocking Network Helper Block For Single-Lane R... Receiver User Clocking Network Helper BlockFor Single-Lane RX Elastic Buffer Bypass Configurations(FRXUSRCLK <> FRXUSRCLK2) Sheet.19 / / Standard Arrow.38 Standard Arrow.39 Sheet.22 Sheet.23 Sheet.24 / / Sheet.25 / / Standard Arrow.8 Standard Arrow.9 Standard Arrow.10 Standard Arrow.11 Connector Dot.387 Connector Dot.20

The helper block holds BUFG_GT primitive(s) in reset when the gtwiz_userclk_rx_reset_in user input is asserted. This reset input should be held High until the source clock input is known to be stable. When the reset input is released, the gtwiz_userclk_rx_active_out user indicator synchronously asserts, indicating an active user clock and allowing dependent helper blocks to proceed.

The helper block can be located either within the core or in the example design per user selection. If included within the core, wiring from the appropriate transceiver channel primitive RXOUTCLK output port(s) to the helper block gtwiz_userclk_rx_srcclk_in input port(s) is also internal to the core, but that clock signal is presented on the core interface as gtwiz_userclk_rx_srcclk_out .


Similarly, wiring between the helper block gtwiz_userclk_rx_usrclk_out and gtwiz_userclk_rx_usrclk2_out output ports and the transceiver channel primitives is internal to the core, but those helper block outputs are also presented on the core interface. If the helper block is located within the example design, then the relevant transceiver channel clock ports are enabled on the core interface so that the necessary signals can cross the core boundary.

If additional clock signals or related ports are required for your application, you can enable the relevant ports on the core instance through the optional ports interface during IP customization. For a description of all receiver user clocking network helper block ports, see Product Specification . See the UltraScale Architecture GTH Transceivers User Guide (UG576) [Ref 1] or UltraScale Architecture GTY Transceivers User Guide (UG578) [Ref 2] for complete documentation on clocking the transceiver primitives.