Receiver Frame (Advanced Section) - 1.7 English

UltraScale FPGAs Transceivers Wizard LogiCORE IP Product Guide (PG182)

Document ID
PG182
Release Date
2023-05-17
Version
1.7 English

Advanced serial transceiver receiver settings are customized by options in the collapsible portion of the receiver frame. Click the title to expand the section.

Insertion loss at Nyquist (dB). Specify the insertion loss of the channel between the transmitter and receiver at the Nyquist frequency in dB.

Equalization mode. Select between decision feedback equalization (DFE) mode and low-power mode (LPM) for the receiver equalization. When the Auto option is selected, the mode is set automatically based on the channel insertion loss, where a value greater than 14 dB causes DFE to be used, otherwise LPM is used. Refer to the UltraScale Architecture GTH Transceivers User Guide (UG576) [Ref 1] or the UltraScale Architecture GTY Transceivers User Guide (UG578) [Ref 2] for further guidance.

Link coupling. Options are AC and DC. Select AC if external AC coupling is enabled in the application, and DC otherwise.

Termination. Select the receiver termination voltage. Your choice of termination should depend on the protocol and its link coupling.

Programmable termination voltage (mV). When termination is set to programmable, select the termination voltage in mV.

PPM offset between receiver and transmitter. Specify the offset between received data and transmitter data in PPM. For example, if your protocol specifies ±100 ppm, you would enter 200 in this field. This offset affects the receiver CDR settings.

Spread spectrum clocking. Specify the spread spectrum clocking (SSC) modulation in PPM. SSC affects the receiver CDR settings.

Enable Out of Band signaling (OOB)/Electrical Idle. Select this option to enable Out of Band (OOB) signaling/Electrical Idle. Availability is subject to the supported receiver line rate, data decoding, reference clock frequency, termination, programmable termination value, and link coupling selections.