Various customization options relating to receiver clock correction are presented in this collapsible section. Click the title to expand the section. Note that, if
RXOUTCLK
source is selected as
RXOUTCLKPMA
which in turn drives
RXUSRCLK/RXUSRCLK2
, then clock correction would do nothing. For more information, see the UltraScale Architecture GTH Transceivers User Guide (UG576)
[Ref 1]
or the
UltraScale Architecture GTY Transceivers User Guide
(UG578)
[Ref 2]
.
• Enable and select number of sequences to use . Select whether to enable receiver clock correction and if enabled, how many clock correction sequences to use. Possible options are No clock correction, 1, or 2 sequences, but available selections can be limited by receiver data decoding, receiver internal data width, and receiver elastic buffer usage.
• Length of each sequence . When clock correction is used, select the length of each clock correction sequence. Options are 1, 2, and 4 patterns.
• Don’t care . For each pattern of each enabled clock correction sequence, mark the checkbox to indicate that it should be treated as a “don’t care” and always considered as a match within a clock correction sequence.
• Value . For each pattern of each enabled clock correction sequence, specify its bit value.
• K character . For each pattern of each enabled clock correction sequence, mark the checkbox to indicate that it is a K character.
• Inverted disparity . For each pattern of each enabled clock correction sequence, mark the checkbox to indicate that it uses inverted disparity to signify a control character by deliberate error.
• Periodicity of the sequence (in bytes) . Specify the separation between clock correction sequences, in bytes.
• Keep idle . Specify whether at least one clock correction sequence is kept in the data stream for every continuous stream of clock correction sequences received. Options are Enable or Disable.
• Precedence . Specify whether clock correction takes precedence over channel bonding when both operations are triggered at the same time. Options are Enable or Disable.
•
Minimum repetition
. Specify the number of
RXUSRCLK
cycles following a clock correction during which the elastic buffer is not permitted to execute another clock correction. Legal options are 0 (for no limit), or 1 to 31 cycles.