The receiver buffer bypass controller helper block contains a user interface and a transceiver interface. The user interface provides a simple means of initiating and monitoring the status of the transceiver receiver buffer bypass procedure. The transceiver interface implements the signaling required to control the transceiver primitive buffer bypass sequence.
Receiver buffer bypass helper block user interface ports can be identified by the prefix gtwiz_buffbypass_rx_. For guidance on the usage of the receiver buffer bypass controller helper block, see
Designing with the Core
.
The receiver buffer bypass controller helper block user interface ports described in
Table: Receiver Buffer Bypass Controller Helper Block User Interface Ports on Core (Helper Block in Core)
are present on the Wizard IP core instance when it is configured to locate the receiver buffer bypass controller helper block in the core. The ports are also present on the helper block itself, directly accessible when the helper block is located in the example design.
In this configuration, the helper block clock port
gtwiz_buffbypass_rx_clk_in
is driven internally to the core by the same source that drives
RXUSRCLK2
of the receiver master channel and is therefore not exposed. When the single-lane buffer bypass procedure is used, one instance of the helper block exists per transceiver channel. The width of each port scales by this factor and each helper block instance is clocked by the same source that drives
RXUSRCLK2
of the associated channel.
Table: Receiver Buffer Bypass Controller Helper Block User Interface Ports on Core (Helper Block in Core)
|
Name
|
Direction
|
Width
|
Clock Domain
|
Description
|
|
gtwiz_buffbypass_rx_reset_in
|
Input
|
1
|
gtwiz_buffbypass_rx_clk_in
|
User signal to reset the logic within the helper block. An active-High, synchronous pulse should be provided immediately after RXUSRCLK2 stabilizes for all transceiver channels.
|
|
gtwiz_buffbypass_rx_start_user_in
|
Input
|
1
|
gtwiz_buffbypass_rx_clk_in
|
Active-High user signal that is synchronously pulsed to force the receiver buffer bypass procedure to restart. Hold Low when not used.
|
|
gtwiz_buffbypass_rx_done_out
|
Output
|
1
|
gtwiz_buffbypass_rx_clk_in
|
Active-High indicates that the receiver buffer bypass procedure has completed.
|
|
gtwiz_buffbypass_rx_error_out
|
Output
|
1
|
gtwiz_buffbypass_rx_clk_in
|
Active-High indicates that the receiver buffer bypass helper block encountered an error condition.
|
The receiver buffer bypass controller helper block user interface ports described in
Table: Other Receiver Buffer Bypass Controller Helper Block User Interface Ports (Helper Block in Example Design)
are not present on the core instance but are present on the receiver buffer bypass controller helper block itself when it is included in the example design.
Table:
Other Receiver Buffer Bypass Controller Helper Block User Interface Ports (Helper Block in Example Design)
|
Name
|
Direction
|
Width
|
Clock Domain
|
Description
|
|
gtwiz_buffbypass_rx_clk_in
|
Input
|
1
|
|
Transceiver primitive-based clock used to control the receiver buffer bypass controller helper block. Must be driven by the same source that drives RXUSRCLK2 of the receiver master channel.
|
|
gtwiz_buffbypass_rx_resetdone_in
|
Input
|
1
|
Async
|
Active-High indication that the receiver reset sequence has been completed, which allows the buffer bypass procedure to begin.
|
The receiver buffer bypass controller helper block transceiver interface ports described in
Table: Receiver Buffer Bypass Controller Helper Block Transceiver Interface Ports
connect the receiver buffer bypass controller helper block to transceiver primitives. When the helper block is located within the core, these connections are internal, and the transceiver primitive inputs that are driven by helper block outputs cannot be enabled as optional ports on the core instance. Inversely, when the helper block is located in the example design, the connections cross the core boundary, so the transceiver primitive ports that connect to the helper block are enabled by necessity.
To implement the multi-lane buffer bypass procedure, the width of each port scales with the number of transceiver channels that the receiver buffer bypass controller helper block interfaces to. When the single-lane buffer bypass procedure is used, one instance of the helper block exists per transceiver channel, so the scaling factor is 1.
Table:
Receiver Buffer Bypass Controller Helper Block Transceiver Interface Ports
|
Name
|
Direction
|
Width
|
Clock Domain
|
Description
|
|
rxphaligndone_in
|
Input
|
1 × Num. channels
|
Async
|
Connects to RXPHALIGNDONE of transceiver channel primitives
|
|
rxdlysresetdone_in
|
Input
|
1 × Num. channels
|
Async
|
Connects to RXDLYSRESETDONE of transceiver channel primitives
|
|
rxsyncout_in
|
Input
|
1 × Num. channels
|
Async
|
Connects to RXSYNCOUT of transceiver channel primitives
|
|
rxsyncdone_in
|
Input
|
1 × Num. channels
|
Async
|
Connects to RXSYNCDONE of transceiver channel primitives
|
|
rxphdlyreset_out
|
Output
|
1 × Num. channels
|
Tied off
|
Connects to RXPHDLYRESET of transceiver channel primitives
|
|
rxphalign_out
|
Output
|
1 × Num. channels
|
Tied off
|
Connects to RXPHALIGN of transceiver channel primitives
|
|
rxphalignen_out
|
Output
|
1 × Num. channels
|
Tied off
|
Connects to RXPHALIGNEN of transceiver channel primitives
|
|
rxphdlypd_out
|
Output
|
1 × Num. channels
|
Tied off
|
Connects to RXPHDLYPD of transceiver channel primitives
|
|
rxphovrden_out
|
Output
|
1 × Num. channels
|
Tied off
|
Connects to RXPHOVRDEN of transceiver channel primitives
|
|
rxdlysreset_out
|
Output
|
1 × Num. channels
|
gtwiz_buffbypass_rx_clk_in (used asynchronously)
|
Connects to RXDLYSRESET of transceiver channel primitives
|
|
rxdlybypass_out
|
Output
|
1 × Num. channels
|
Tied off
|
Connects to RXDLYBYPASS of transceiver channel primitives
|
|
rxdlyen_out
|
Output
|
1 × Num. channels
|
Tied off
|
Connects to RXDLYEN of transceiver channel primitives
|
|
rxdlyovrden_out
|
Output
|
1 × Num. channels
|
Tied off
|
Connects to RXDLYOVRDEN of transceiver channel primitives
|
|
rxsyncmode_out
|
Output
|
1 × Num. channels
|
Tied off
|
Connects to RXSYNCMODE of transceiver channel primitives
|
|
rxsyncallin_out
|
Output
|
1 × Num. channels
|
Async
|
Connects to RXSYNCALLIN of transceiver channel primitives
|
|
rxsyncin_out
|
Output
|
1 × Num. channels
|
Tied off
|
Connects to RXSYNCIN of transceiver channel primitives
|