The receiver buffer bypass controller helper block automates the buffer bypass procedure, which must be performed when the serial transceiver receiver elastic buffer is not used. The helper block implements the auto-mode buffer bypass sequence. When the wizard is configured to bypass the receiver elastic buffer, the following takes place:
• If multi-lane buffer bypass mode is enabled, one instance of the helper block is delivered and implements the multi-lane buffer bypass procedure. In this case, the user interface port width is not scaled, while the transceiver interface is scaled to the number of channel primitives in the core.
• If single-lane buffer bypass mode is enabled, an instance of the helper block is delivered for, and wired to each transceiver channel primitive instance. In this case, the user interface port width scales with the number of helper blocks, while the transceiver interface connects to its corresponding channel primitive only.
The helper block user interface provides you with a simple means of initiating and monitoring the status of the receiver buffer bypass procedure. Its transceiver interface connects to transceiver channel primitive(s) within the core.
The helper block is synchronously reset when the
gtwiz_buffbypass_rx_reset_in
user input is asserted. This signal should be released as soon as
RXUSRCLK2
of the receiver master channel (for multi-lane buffer bypass configurations), or
RXUSRCLK2
of the corresponding channel (for single-lane buffer bypass configurations) is stable, and before the receiver datapath reset sequence completes for all channels. By default, the reset helper block
gtwiz_reset_rx_done_out
output is wired to the receiver buffer bypass controller helper block
gtwiz_buffbypass_rx_resetdone_in
input. A rising edge on this port automatically initiates the receiver buffer bypass procedure.
When the receiver buffer bypass procedure completes, the
gtwiz_buffbypass_rx_done_out
user indicator is asserted and the
gtwiz_buffbypass_rx_error_out
indicator is set. The two user interface outputs should be considered together to decode the result of the buffer bypass procedure, as shown in
Table: Transmitter Buffer Bypass Controller Helper Block Completion Result Encoding
.
You can force the receiver buffer bypass controller helper block to initiate the buffer bypass procedure at any time after the helper block has been reset and the initial procedure has been completed by pulsing the
gtwiz_buffbypass_rx_start_user_in
user input.
The helper block can be located either within the core or in the example design per user selection. Depending on its location and the location of other helper blocks, the relevant ports are enabled on the core interface so that the necessary signals can cross the core boundary.
If you choose to locate the helper block within the core but also wish to observe individual transceiver primitive buffer bypass status signals, you can enable the relevant ports on the core instance through the optional ports interface during IP customization.
See Product Specification , for a description of all receiver buffer bypass controller helper block ports. See the UltraScale Architecture GTH Transceivers User Guide (UG576) [Ref 1] or UltraScale Architecture GTY Transceivers User Guide (UG578) [Ref 2] for complete documentation on bypassing the receiver elastic buffer in transceiver primitives.