An example design can be generated for any customization of the AMD UltraScale ™ FPGAs Transceivers Wizard IP core. After you customize and generate a core instance, choose the Open IP Example Design Vivado Integrated Design Environment (IDE) option for that instance. A separate Vivado project opens with the wizard example design as the top-level module. The example design instantiates the customized core.
The purpose of the Wizard IP example design is to:
• Provide a simple demonstration of the customized core instance operating in simulation or in hardware through the use of a link status indicator based on PRBS generators and checkers.
• Provide a starting point for integrating the customized core into your system, including reference clock buffers and example system-level constraints.
• Simplify hardware bring-up and debug through the inclusion of a virtual input/output (VIO) core instance that probes key debug signals and can be re-customized as needed.
• Provide a variety of convenience features including instantiation and use of helper blocks that were not located in the core, and per-channel vector-slicing.
The example design contains configurable PRBS generator and checker modules per transceiver channel that enable simple data integrity testing, and resulting link status reporting. As described in Test Bench , an included self-checking test bench simulates the example design in loopback, checking for link maintenance. The example design is also synthesizable so it can be used to check for data integrity and resulting link in hardware, either through loopback or connection to a suitable link partner. A VIO core instance probes key status signals, drives basic control signals, and reduces reliance on hardware I/O interaction.
RECOMMENDED: As the primary means of demonstrating the customized core, AMD recommends that you use the example design to familiarize yourself with the basic usage and behavior of the Wizard IP core.