Depending on IP customization choices including helper block locations, synchronizers can be instantiated within the core or the example design in order to facilitate clock domain crossing of individual signals. When synchronizers or other ignorable asynchronous paths are present, false path constraints are included in the core-level XDC file or in the example design XDC file (as appropriate) for those arbitrary latency paths. Some possible commands for each XDC file are as follows:
set_false_path -to [get_cells -hierarchical -filter {NAME =~ *bit_synchronizer*inst/i_in_meta_reg}]
set_false_path -to [get_cells -hierarchical -filter {NAME =~ *reset_synchronizer*inst/rst_in_*_reg}
set_false_path -to [get_cells -hierarchical -filter {NAME =~ *gtwiz_userclk_tx_inst/*gtwiz_userclk_tx_active_*_reg}]
set_false_path -to [get_cells -hierarchical -filter {NAME =~ *gtwiz_userclk_rx_inst/*gtwiz_userclk_rx_active_*_reg}]