This frame is labeled as “Expose additional ports by Functionality, for advanced feature usage” in the Customize IP dialog box. The optional port enablement interface allows additional transceiver channel and transceiver common primitive ports to be exposed on the core interface. See the UltraScale Architecture GTH Transceivers User Guide (UG576) [Ref 1] or UltraScale Architecture GTY Transceivers User Guide (UG578) [Ref 2] for details on each available transceiver primitive port.
• All Ports. All wizard ports are presented for optional enablement in this highlighted, collapsible section. Click the title to expand the section and display the All Ports table. Ordering is alphabetical by port name, and organized according to port direction. The Name column of the table shows the Wizard IP core interface name for each port, while the Information column indicates the transceiver primitive type and mapping of that port (for non-helper block ports). Mark the checkbox for a given port in the Enable column to expose that port on the core interface. The IP symbol is updated to reflect the enabled ports. The search field can be used to search text within the All Ports collapsible section. Port enablement restrictions of the All Ports table are as follows:
° Helper block port enablement cannot be directly controlled and is a function of helper block availability and location only.
° Transceiver primitive input ports that are driven within the core instance, usually as a result of locating a helper block within the core, cannot be enabled.
° Ports corresponding to transceiver common primitives cannot be enabled if the core instance does not instantiate any transceiver common primitives.
° Ports unique to transceiver types that are different from the selected transceiver type cannot be enabled.
• Other groups. Collapsible groups other than All Ports categorize the wizard ports according to specific transceiver functionality. Click the title of a group to expand its section. To easily identify and enable the ports required for your application, groups are organized and named according to chapters within the UltraScale Architecture GTH Transceivers User Guide (UG576) [Ref 1] or UltraScale Architecture GTY Transceivers User Guide (UG578) [Ref 2] . In addition, a Transceiver-based IP Debug Ports group is provided to organize frequently used debug ports. Mark the checkbox for a given port to expose that port on the core interface. The IP symbol is updated to reflect the enabled ports. Port enablement restrictions in other groups are as follows:
° Transceiver primitive input ports that are driven within the core instance, usually as a result of locating a helper block within the core, cannot be enabled.
° Ports corresponding to transceiver common primitives cannot be enabled if the core instance does not instantiate any transceiver common primitives.
° Ports unique to transceiver types that are different from the selected transceiver type cannot be enabled.
• ENABLE_COMMON_USRCLK :
° Default value =>0
° Setting 0 => TXUSRCLK/TXUSRCLK2 source is TXOUTCLK and RXUSRCLK/RXUSRCLK2 source is RXOUTCLK
° Setting 1 => TXUSRCLK/TXUSRCLK2/RXUSRCLK/RXUSRCLK2 source is RXOUTCLK
° Setting 2 => TXUSRCLK/TXUSRCLK2/RXUSRCLK/RXUSRCLK2 source is TXOUTCLK
• This advanced option is valid only if both the TX and the RX clocking helper blocks are configured as being inside the CORE option, and the BufferBypass controllers are also inside the CORE. If any of these helper blocks are configured as EXAMPLE_DESIGN, this parameter takes a default value of 0. In cases where clocking helper blocks are outside the Wizard CORE, you could manually instantiate TX alone or RX alone as per your clocking requirement.
• The ENABLE_COMMON_USRCLK option feature is rarely used. As a result, it is not accessible from the wizard. This parameter cannot be passed through the core wrapper. Therefore, users need to configure it directly in the RTL.