Maximum Frequencies - 1.7 English

For the serial transceiver switching characteristics and the serial transceiver user clock switching characteristics, see the applicable data sheet for your device:

• ​ Kintex UltraScale Architecture Data Sheet: DC and AC Switching Characteristics (DS892) [Ref 3]

• ​ Virtex UltraScale Architecture Data Sheet: DC and AC Switching Characteristics (DS893) [Ref 4]

• ​ Zynq UltraScale+ MPSoC Data Sheet: DC and AC Switching Characteristics (DS925) [Ref 5]

• ​ Kintex UltraScale+ FPGAs Data Sheet: DC and AC Switching Characteristics (DS922) [Ref 6]

• ​ Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics (DS923) [Ref 7]

You must use the frequency ranges specified by these documents for proper transceiver and core operation.

IMPORTANT: A free-running clock input, gtwiz_reset_clk_freerun_in , is required by the reset controller helper block to reset the transceiver primitives. In GTH transceiver core configurations targeting engineering sample (ES1 or ES2) UltraScale devices and GTHE4, GTYE4 UltraScale+ devices where the CPLL is used, this clock must also drive each bit of the drpclk_in port. As shown in Table: Free-Running Clock Maximum Frequency , the maximum frequency of this clock must not exceed either an upper bound or the slowest of the transceiver channels' user clock frequencies for the core as customized. The precise frequency of the free-running clock which is specified during IP customization should not change because of the dependencies in the CPLL calibration block. For more details, see Customizing and Generating the Core . The free-running clock must not be derived from user clocks or their sources.