Link Status Logic - 1.7 English

UltraScale FPGAs Transceivers Wizard LogiCORE IP Product Guide (PG182)
Document ID
PG182
Release Date
2023-05-17
Version
1.7 English

The wizard example design instantiates an independent PRBS data checker module for each enabled transceiver channel. The combined and synchronized match signal is used by the link status logic, which produces a link status indicator using a simple state machine within the wizard example design. To best represent the link health of the example design system, the link status indicator follows the combined PRBS match value but is resilient to occasional mismatches such as infrequent bit errors.


The link status state machine uses a leaky bucket algorithm to accumulate multiple consecutive clock cycles of combined PRBS matches, incrementing a link counter to its prescribed maximum before reporting that the link is up (indicated by link_status_out = 1). After the link is up, any PRBS mismatches cause a more rapid decrease in the link counter, such that bursts of mismatches or independent mismatches in close proximity quickly reduce the link counter to its prescribed minimum where the link is reported as down (indicated by link_status_out = 0). The logic operates continually, and therefore automatically attempts to recover from transient mismatches or regain link upon its loss. This Figure illustrates the behavior of the link counter and resulting link status in response to various PRBS checker conditions.

Figure: Link Counter and Link Status in Response to Various PRBS Checker Conditions

Page-1 Standard Arrow.1 Sheet.2 Start of Operation Start of Operation Sheet.3 Time Time Sheet.4 Link counter increments on each subsequent clock cycle when P... Link counter increments on each subsequent clock cycle when PRBS checker matches Standard Arrow.5 Sheet.6 MAX MAX Sheet.7 Link Counter Value Link Counter Value Sheet.8 MIN MIN Sheet.9 PRBS checker begins to indicate matches PRBS checker beginsto indicate matches Arrow Standard Right.10 Sheet.11 Sheet.12 Link counter reaches terminal count; link is declared to be UP Link counter reachesterminal count; link is declared to be UP Sheet.13 Single PRBS mismatch (e.g., due to bit error) reduces link co... Single PRBS mismatch (e.g., due to bit error) reduces link count by just over half its value, but link remains UP Sheet.14 Link counter again reaches terminal count Link counter againreaches terminal count Sheet.15 PRBS checker again begins to indicate matches; link remains D... PRBS checker again begins to indicate matches; link remains DOWNas link counter increments Sheet.16 Link Status Link Status Standard Arrow.17 Sheet.18 * * Sheet.19 Sheet.20 * * Sheet.21 DOWN DOWN Sheet.22 UP UP Sheet.23 DOWN DOWN Standard Arrow.24 Sheet.25 PRBS mismatches in close proximity reduce link count to its f... PRBS mismatches in close proximity reduce link count to its floor; link is declared to be DOWN Sheet.26 Sheet.27 Sheet.28 Sheet.29 Sheet.30 Sheet.31 X14551 X14551 Sheet.32 Sheet.33

Whenever the link is down, including at the start of operation, the sticky link down indicator link_down_latched_out is set to 1. It can only be reset by assertion of the link_down_latched_reset_in input.

A simple use of the link status interface in hardware is to map link_status_out and link_down_latched_out to active-High LEDs, and link_down_latched_reset_in to an active-High pushbutton. The link_status_out LED gives a rough estimation of link behavior, while even momentary loss of link is visible due to the sticky behavior of link_down_latched_out lighting the LED. The link_down_latched_reset_in pushbutton clears link_down_latched_out , turning off its LED as long as the link remains up. These link status interface signals are also connected to the VIO core instance by default.