The example design is the recommended means of simulating or implementing an instance of the Wizard IP core outside the context of your own system. It can also prove useful as a starting point for integrating the core into your system. However, it is quite simplistic, and the following limitations should be understood:
• The example design does not implement specific protocols to generate or check data. For example, while the example stimulus module does support TX Gearbox data encoding configurations and the example checking module does support RX Gearbox data decoding configurations to interface to the transceiver channel primitives, they do not implement true 64B/66B or 64B/67B data coding. Fundamentally, raw PRBS data is generated and checked.
• When the example design is simulated using the provided test bench, each transceiver channel is looped back from the serial data transmitter to the receiver. As such, data integrity can only be properly checked if the transmitter and receiver are configured for the same line rate and to use the same data coding. No transcoding or rate adjustment schemes are used. If the transmitter and receiver line rates or data coding are configured differently from one another in your system, you might wish to cross-couple two appropriately-customized core instances and check for data integrity in hardware or in your own test bench. In such a setup, the transmitter of core instance A is rate- and coding-matched to the receiver of core instance B, and vice versa.