Hierarchy and Structure - 1.7 English

The hierarchy and simplified representation of the structure of the Wizard IP example design is illustrated in This Figure .

The example design instantiates the customized core instance. The core instance contains one or more transceiver channel primitives and, depending on customization choices, can instantiate one or more transceiver common primitives and one or more helper blocks. Portion A of the figure represents a helper block included within the core instance.

The lowest level of example design hierarchy is the example design wrapper. The purpose of the example design wrapper is to instantiate only the customized core and any helper blocks that you included in the example design. By including only those resources and no additional demonstration logic, the example design wrapper can be integrated into your project with no or minimal modification required. Portion B of the figure represents a helper block instantiated within the example design wrapper. Enabled ports of the core instance that do not directly interface to helper block B are routed through to the next level of example design hierarchy.

The example design top-level module instantiates the example design wrapper and is the top-level module of the Vivado IP example project. The top-level module serves many purposes. Portion C of the figure represents the different ways that ports enabled on the core and exposed through the example design wrapper are handled in the example design top-level module. Ports that were optionally enabled or otherwise enabled but are not directly used in the example design are tied to their appropriate values (per the core customization). A small number of ports that must be driven internally to the example design for purposes of example design operation are driven by some logic function to produce the necessary value. A small number of ports are also connected to the top-level example design I/O.

An example stimulus module and an example checking module are each instantiated for each transceiver channel instance. As shown in portion D of the figure, these modules include a PRBS block that is customized for data generation or checking as appropriate, as well as a minimal amount of additional logic sufficient to interface to the selected transmitter data encoding and receiver data decoding formats of the transceiver channels.

Note: The example stimulus and example checking modules fundamentally transmit and check raw PRBS data, and do not implement higher-level protocols to encapsulate that raw data.

Because independent example stimulus and checking modules exist per channel, an aggregate pattern match status across all modules is needed. A small amount of logic in the example design top-level module combines the match status from all example checking modules into a single “match all” signal. This signal is then used in a simple link status state machine to indicate the health of the PRBS checker-based link while remaining resilient to occasional bit errors. A sticky link down indicator is set any time the link status signal de-asserts, and an accompanying reset signal clears that sticky link down indicator. Together, these three signals are sufficient to monitor data integrity-based link status across all transceiver channels in an abstract fashion, including mapping the top-level I/O to two LEDs and one pushbutton on a PCB. To reduce reliance on hardware I/O interaction and simplify example design bring-up and debug, a VIO core instance also connects to these top-level signals and other key control and status signals. The VIO core can be re-customized and connected to other signals as needed.

Additionally, an initialization state machine provides demonstration logic that interacts with and enhances the reset controller helper block to assist with successful system bring-up. See Link Status and Initialization for more details on these features.

As shown in portion E of the figure, a dedicated transceiver reference clock differential buffer (IBUFDS_GTE3 or IBUFDS_GTE4 primitive) is instantiated for each reference clock source that was specified in the Physical Resources tab of the Customize IP dialog box. Differential clock input ports drive each buffer instance, which in turn is wired to all the transceiver channel or transceiver common primitives it was specified to drive. If you wish to use different connectivity in your system, re-customize the core and select different transceiver reference clock locations in the Customize IP dialog box, rather than modifying the clock connectivity, to properly adjust both the wiring and the transceiver primitive location constraints.

The ports shown in Table: Example Design Top-Level Ports are present on the example design top-level module, and are therefore package pins in the example project.