The design guidelines for the wizard core largely reflect those of the serial transceivers instantiated by the Wizard. It is important to understand the general usage and specific procedures that are required for the correct operation of serial transceivers in your system. See the UltraScale Architecture GTH Transceivers User Guide (UG576) [Ref 1] or UltraScale Architecture GTY Transceivers User Guide (UG578) [Ref 2] for details.
The AMD UltraScale ™ FPGAs Transceivers Wizard provides a highly flexible AMD Vivado ™ Integrated Design Environment (IDE)-driven customization flow, which in addition to basic customization of transceiver use modes, also includes a physical resource site selection interface, an optional port enablement interface, and helper block location choices. The result is a core instance that addresses the specific needs of your application. As such, Wizard IP core instances do not require manual modification and should not be edited. AMD cannot guarantee timing, functionality, or support if modifications are made to any output products of the generated core.