Specify the frequency of the required free-running clock that will be provided to bring up the core and to clock various helper blocks. An accurate frequency is required to construct clock constraints and parameterize certain design modules. For GTH transceiver configurations that target engineering sample (ES1 or ES2) UltraScale devices and that use the CPLL, this clock must also be used for the transceiver channel DRP interface. See Performance for maximum frequency guidance.