• Transceiver configuration presets for industry standards
• Simple and intuitive feature selection flow
• Automatically sets transceiver parameters
• Advanced options to tune the performance
• Transceiver site and reference clock selection interface
• Available helper blocks to simplify common or complex transceiver usage
• Optional exposure of any transceiver port depending upon the selected configuration
• Example design with configurable PRBS generator, checker, and link status indicator to demonstrate functionality in simulation and hardware
• Flexible placement of each helper block within the core for simplicity or within example design for user customization
• Support for UltraScale and UltraScale+ ™ architectures
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LogiCORE ™ IP Facts Table |
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Core Specifics |
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Supported Device Family (1) |
AMD UltraScale+ ™ Families AMD Kintex ™ UltraScale AMD Virtex ™ UltraScale |
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Supported User Interfaces |
Not Applicable |
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Resources |
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Provided with Core |
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Design Files |
RTL |
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Example Design |
Verilog |
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Test Bench |
Verilog |
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Constraints File |
Xilinx Design Constraints (XDC) |
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Simulation Model |
Source HDL with SecureIP transceiver simulation models |
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Supported
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Not Provided |
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Tested Design Flows |
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Design Entry |
AMD Vivado ™ Design Suite |
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Simulation |
For supported simulators, see the Vivado Design Suite User Guide: Release Notes, Installation, and Licensing [Ref 14] . |
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Synthesis |
Vivado Synthesis |
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Support |
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Release Notes and Known Issues |
Master Answer Record: 57487 |
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All Vivado IP Change Logs |
Master Vivado IP Change Logs: 72775 |
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Notes:
1. For a complete list of supported devices, see the Vivado IP catalog. |
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