The wizard provides the following features:
• Customization flow driven by the Vivado Integrated Design Environment (IDE), provides high-level choices that configure supported transceiver features and automatically set primitive parameters as per the requirements.
• Variety of transceiver configuration preset selections to target industry standards.
• Advanced configuration options to tune transceiver performance.
• Transceiver site, reference clock, and recovered clock selection interface for enabling one or more transceiver channels and adherence to clock routing restrictions.
• Configuration interface, an optional feature for comma detection and alignment, channel bonding, clock correction, buffer control, advanced clocking, and some protocol-specific features.
• Available helper blocks to simplify common or complex transceiver usage, and the choice to either include or exclude each helper block from the core.
° Helper blocks excluded from the core are delivered as user-customizable starting points within the example design.
• Ability to locate enabled transceiver common primitives either within the core or in the example design, and connectivity to simplify resource sharing across multiple cores.
• Optional port enablement interface provides the ability to expose any transceiver primitive port as a top-level core port. However, these ports should not be in conflict with any dependent helper core location and configuration of the wizard.
• Synthesizable example design with configurable pseudo-random binary sequence (PRBS) data generator, checker, and link status indicator logic to quickly demonstrate core and transceiver functionality in simulation and hardware:
- Simulation test bench that monitors example design PRBS lock in loopback, and indicates resulting link status.
- Virtual input/output (VIO) core instance that simplifies basic example design hardware bring-up, and key debug signal probing.
- Additional convenience features, including differential reference clock buffer instantiation and wiring, and per-channel vector slicing.
• Core and example design level Design constraints (DC) files with timing, location, and other constraints as necessary for the selected configuration.