When an example design is generated for an instance of the Wizard IP core, an XDC file is generated for that example project. The example design XDC file contains the required top-level constraints for the full design, which include:
• I/O location constraints for each instantiated transceiver differential reference clock buffer.
• Placeholder I/O location constraints, which serve as commented templates to constrain the location of top-level I/O as appropriate for your system.
• System-level clock period constraints on the free-running clock used for system bring-up, and on the transceiver reference clocks differential inputs.
• False path constraints for synchronizer modules or other false paths that are included in the example design.
The example design XDC is necessary to properly constrain elements within the example design, but it can also be used as a starting point for the development of your system-level constraints. The constraints in the example design XDC do not overlap with those in the core-level XDC.