In UltraScale+ GTH/GTY transceiver CPLL may not be able to reliably lock in the following circumstances:
• After configuration
• Removing/re-applying reference clock
• Asserting/de-asserting CPLLPD
In the failure state, the CPLL may freeze at an invalid output frequency and the CPLLLOCK signal may incorrectly be set high. The solution for this issue is to include the CPLL Calibration block. The following user parameters are added to the UltraScale GT Wizard IP without the GUI presence for this purpose:
•
INCLUDE_CPLL_CAL
:
° Default Value => 2: For CPLL configured IPs, the CPLL Calibration block will be enabled internally by default for GTHE4 and GTYE4.
° setting 1 => Includes the CPLL Calibration block,
° setting 0 => Excludes the CPLL Calibration block.
•
SIM_CPLL_CAL_BYPASS
:
° Default Value => 1
° setting 0 => Continues to use the large counters in CPLL Calibration block and mimics the hardware behavior
° setting 1 => Bypasses some of the counters in CPLL Calibration block through the usage of synthesis translate on/off pragmas and improves functional simulation time.
To enable the CPLL Calibration block for GTYE4/GTHE4 UltraScale+ devices, set the value of
INCLUDE_CPLL_CAL
to 1 while generating the IP through Tcl customization. This additional block could result in higher simulation times. This is because CPLL calibration block evaluates the frequency at which the CPLL lock is achieved. To bypass this block to reduce functional simulation time, set the
SIM_CPLL_CAL_BYPASS
user parameter to 1 during IP customization.
Note: This will not have any effect on post-synthesis simulations and hardware functionality.
The CPLL Calibration block is now enhanced to work with both TX alone or RX alone for advanced use cases. When Both TX alone or TX + RX are using CPLL, then only the TX CPLL Calibration block would be applicable, while in the use case where TX is not CPLL and RX is CPLL (t
xpllclksel_in!
= 0 and
rxpllclksel_in
==0), then RX CPLL Calibration block is used. The choice of TX/RX CPLL calibration block to be used is done based on the user configuration entered in IP customization GUI. The below CPLL calibration block ports are exposed only when the
INCLUDE_CPLL_CAL
user parameter is set to 1, the default values corresponding to the line-rate are obtained by open-example design step or by following the equation specified in the description field. If you set the value of
INCLUDE_CPLL_CAL
to 2, the HDL logic inside the wizard drives the relevant ports internally for configuration during IP customization.
AMD recommends that the
INCLUDE_CPLL_CAL
parameter be set to 1 and appropriate values be driven on the ports shown in
Table: CPLL Calibration Block Additional Ports
when the GT parent IP intends to perform dynamic line rate switching. For more information and guidance on the rate usage of these ports, see AMD Answer:
AR# 70485
.
|
Direction |
Description |
|
|---|---|---|
|
USER_TXOUTCLK_BUFG_CE_IN gtwiz_gthe4_cpll_cal_bufg_ce_in gtwiz_gtye4_cpll_cal_bufg_ce_in |
Input |
CE for BUFG_GT for TX clocking |
|
TXOUTCLK_PERIOD_IN[17:0] gtwiz_gthe4_cpll_cal_txoutclk_period_in gtwiz_gtye4_cpll_cal_txoutclk_period_in |
Input |
Calculated as:
Set the value of FREQ_COUNT_WINDOW to 16,000. FREQ_CLKIN is the frequency of gtwiz_reset_clk_freerun_in , referred to as the FREERUN_FREQUENCY user parameter, on the Physical Resources tab of the UltraScale GT Wizard as shown in This Figure . This frequency is referred to as the free-running and DRP clock frequency. CPLL_VCO_RATE is the fPLLClkout , which is the PLL output frequency in MHz as described in the UltraScale Architecture GTH Transceivers User Guide (UG576) [Ref 1] and UltraScale Architecture GTY Transceivers User Guide (UG578) [Ref 2] . For CPLL based rate switching requirements, the easiest way to get the expected values is to generate example designs for each of the target line rate combinations, as the GT Wizard IP would calculate the target values based on the project parameters and the data-sheet ranges. |
|
CNT_TOL_IN[17:0] gtwiz_gthe4_cpll_cal_cnt_tol_in gtwiz_gtye4_cpll_cal_cnt_tol_in |
Input |
Set to ROUND(0.01*TXOUTCLK_PERIOD_IN) |