This section includes information about using AMD tools to customize and generate the core in the Vivado Design Suite.
You can customize the Wizard IP core for use in your design by specifying values for the various parameters associated with the core using these steps:
1. In the Vivado Design Suite, create a new project or open an existing project that is configured to target one of the supported AMD UltraScale ™ or UltraScale+ ™ devices.
IMPORTANT: It is important to choose the exact part because characteristics such as speed grade, temperature grade, and silicon level affect the available features and performance limits of the serial transceivers. Limitations based on device characteristics are represented by the available choices when customizing the Wizard IP in the Vivado Integrated Design Environment (IDE).
2. Open the IP catalog and select the IP at FPGA Features and Design > I/O Interfaces > UltraScale FPGAs Transceivers Wizard .
3. Double-click the IP or select the Customize IP command from the toolbar or right-click menu to display the Wizard Customize IP dialog box.
Note: This core is not available in the Vivado IP integrator.
For details, see the Vivado Design Suite User Guide: Designing with IP (UG896) [Ref 8] .
Note: Figures in this chapter are illustrations of the Vivado IDE. This layout might vary from the current version.