Each instance of the UltraScale FPGAs Transceivers Wizard core includes a core-level design constraints (XDC) file customized for that instance. The core-level XDC file contains:
• Transceiver location constraints that reflect the transceiver primitive site locations selected during customization of the Physical Resources tab of the Customize IP dialog box.
• Case analysis constraints, as necessary, that direct the Vivado design tools to propagate the correct constraint for the operational TXOUTCLK frequency.
• False path constraints, as necessary, if synchronizer modules or other false paths are included in the core.
The constraints provided in the core-level XDC file are required for proper operation of the core instance. This file is managed by the Vivado design tools and can change to reflect core customization changes or core version upgrades. Do not modify this file. For advanced use cases, if you want to manage GT locations manually, set DISABLE_LOC_XDC user parameter to ‘1’ during IP customization.
Note: GT parent IP could be driving the value of this user parameter as part of the hierarchical instantiation, and using this parameter may not be always possible in a locked IP scenario. If you need to manage the GT locations, AMD recommends that you configure the GT parent IP as GT outside and then customize the UltraScale GT wizard IP based on your design requirement.