The wizard example design provides several convenience features that can be useful when integrating the core instance into your system.
• Any helper blocks that were specified to be included in the example design are instantiated within the example wrapper level of hierarchy. By including only those resources and no additional demonstration logic, the example design wrapper can be useful to integrate in your own project with no, or minimal modification required.
• If the transceiver common was specified to be included in the example design, all enabled transceiver common instances are also localized within the example wrapper level of hierarchy.
• As described in Product Specification , the core provides vectored ports that are concatenations of the corresponding port across enabled transceiver primitives. While this provides a compact and predictable user interface, users might prefer individual signals per transceiver primitive. The example design top-level module provides vector slicing for each enabled port, assigning each slice as appropriate for the signal type. This feature can be used for reference or integrated into your system as desired. Three examples follow, for illustration:
a. If the core instance contains four enabled GTH transceiver channels, their GTHTXP serial data output pins are vectored as gthtxp_out[3:0] on the core interface and mapped to gthtxp_int[3:0] within the example design top-level module. The four bits of the vector are sliced into four per-channel assignments that also map to top-level outputs. The “ch” prefix of each signal indicates a transceiver channel signal type, and the number that follows indicates its index among all enabled transceiver channel primitives:
wire [3:0] gthtxp_int;
assign ch0_gthtxp_out = gthtxp_int[0:0];
assign ch1_gthtxp_out = gthtxp_int[1:1];
assign ch2_gthtxp_out = gthtxp_int[2:2];
assign ch3_gthtxp_out = gthtxp_int[3:3];
b. If the core instance contains three enabled transceiver channels and optionally enables the drpaddr_in port, the 9-bit DRPADDR transceiver channel ports are vectored as drpaddr_in[26:0] on the core interface and mapped to drpaddr_int[26:0] within the example design top-level module. The 27-bits of the vector are sliced into three per-channel assignments that are each set to the same default driver value that the corresponding transceiver primitive port would have been assigned to internally if the port were not exposed on the core interface. If you choose to integrate the vector slicing convenience code into your project, assign the signals as appropriate for your system:
wire [26:0] drpaddr_int;
wire [8:0] ch0_drpaddr_int = 9'b000000000;
wire [8:0] ch1_drpaddr_int = 9'b000000000;
wire [8:0] ch2_drpaddr_int = 9'b000000000;
assign drpaddr_int[8:0] = ch0_drpaddr_int;
assign drpaddr_int[17:9] = ch1_drpaddr_int;
assign drpaddr_int[26:18] = ch2_drpaddr_int;
c. If the core instance contains one enabled transceiver common and optionally enables the qpll0lock_out port, the one-bit QPLL0LOCK transceiver common port is provided as qpll0lock_out[0:0] on the core interface and mapped to qpll0lock_int[0:0] within the example design top-level module. For this single primitive case, the provided vector slicing is equivalent to a renamed signal. The “cm” prefix of each signal indicates a transceiver common signal type, and the number that follows indicates its index among all enabled transceiver common primitives:
wire [0:0] qpll0lock_int;
wire [0:0] cm0_qpll0lock_int;
assign cm0_qpll0lock_int = qpll0lock_int [0:0];
d. Multiple instances of a helper block also results in similar assignments. The “hb” prefix of each signal indicates a helper block signal type, and the number that follows indicates its index among all included helper blocks of that type.
Note: A very small number of uncommonly used transceiver primitive ports are tied off to safe values within the core. If you use the optional port enablement interface to enable access to such a port on the core interface, a warning message with usage instructions is included as a code comment with its vector slicing assignments in the example design top-level module.
• The example design top-level module provides easy access to the reset inputs of the user clocking network helper blocks, and by default, drives them with appropriate signals that indicate clock source stability.