The example design XDC file creates period constraints for the clock inputs that drive the dedicated differential reference clock buffers, which in turn drive the various PLL resources in the core and propagate to the TXOUTCLK and RXOUTCLK pins of each transceiver channel primitive. Where a transceiver channel drives a user clocking network helper block, those derived constraints then propagate through the helper block resources to constrain synchronous paths at the relevant clock frequencies of that user clock network. The correct clock period for each constraint is automatically determined by the wizard. For example, when using a single reference clock buffer in the X0Y0 grid position, a command similar to the following will exist in the example design XDC file:
create_clock -period 6.400 [get_ports mgtrefclk0_x0y0_p]
IMPORTANT: It is important to retain the create_clock command that exists in the example design XDC and is applied to the input of the differential reference clock buffers. This constraint is used to derive the user clocking network constraints.
For GTH transceiver configurations targeting engineering sample (ES1 or ES2) UltraScale devices, and in which the CPLL is used as the PLL type for a given data direction or as the source of the selectable TXOUTCLK frequency, set_case_analysis commands exist within the core-level XDC.
set_case_analysis 0 [get_pins -hierarchical -filter {NAME =~ *gen_channel_container[0].*gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXOUTCLKSEL[2]}]
set_case_analysis 1 [get_pins -hierarchical -filter {NAME =~ *gen_channel_container[0].*gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXOUTCLKSEL[1]}]
set_case_analysis 0 [get_pins -hierarchical -filter {NAME =~ *gen_channel_container[0].*gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXOUTCLKSEL[0]}]
Using the frequency provided during core customization, the example design XDC file creates a period constraint for the free-running clock used for system bring-up. For example:
create_clock -period 10 [get_ports hb_gtwiz_reset_clk_freerun_in]
Additional clock period constraints can be necessary when integrating the Wizard IP core into your system. For example:
• If you enable any optional clock ports on the Wizard IP core interface (for example, the DRP clock), you must appropriately constrain those clocks.
Note: As described in Customizing and Generating the Core , the free-running clock must also be used for the transceiver channel DRP interface clock in GTH transceiver configurations targeting architecture engineering sample (ES1 or ES2) UltraScale devices that use the CPLL.
If you choose not to use the provided user clocking network helper blocks and thus break the path from TXOUTCLK or RXOUTCLK through the appropriate user clocking network helper blocks and to the appropriate transceiver user clocks, you must appropriately constrain the new source of the transceiver user clocks.