Various customization options relating to advanced clocking methodologies and frequencies are present in this collapsible section. Click the title to expand the section.
• Enable secondary QPLL . When either QPLL0 or QPLL1 (but not both) are used to clock the transmitter and/or receiver, the remaining QPLL is unused in the core as configured. Enable this option to allow customization of the secondary QPLL in the transceiver common for use in a different core. Refer to Transceiver Common Primitive for transceiver common sharing approaches.
• Line rate of second core (Gbps) . Enter the transmitter and/or receiver line rate, in gigabits per second, for the core that will utilize the secondary QPLL instantiated by this core. The available range depends on transceiver type and can be limited by the selected device.
• QPLL Fractional-N options . For configurations targeting a secondary QPLL in a device which supports the fractional-N feedback divider, enter a Requested reference clock (MHz) value and click the Calc button. This action populates the Actual re ference cl ock (MHz) field with a variety of supported reference clock frequencies based on the requested value. In most cases, the requested frequency is available for selection. The calculation also populates the Fractional part of QPLL feedback divider field with the numerator of the fractional part of the QPLL feedback divider used to clock the secondary QPLL-driven datapath. This value can be manually tweaked to fine-tune the available Actual re ference cl ock (MHz) selections for advanced use cases. Possible values are 0 through 16777215, where 0 disables fractional-N operation. Changing this field updates the available Actual re ference cl ock (MHz) selections.
• Actual reference clock frequency (MHz) . Select the desired frequency from among all compatible frequencies for the reference clock that will be provided to the secondary QPLL to achieve the selected transmitter and/or line rate used in the second core.
• Enable selectable TXOUTCLK frequency . When the TX programmable divider (TXPROGDIVCLK) is selected as the TXOUTCLK source, it might be possible to choose a non-default frequency for that clock, or to choose a different clock source for the TX programmable divider. Enable this option to select from among the available choices that are compatible with the core as configured.
• Programmable divider clock source . Select the PLL clock source for the TX programmable divider. Options include the PLL type chosen for the transmitter, and the CPLL if certain frequency relationships are met.
Note: If a PLL type is selected that is different than the PLL type chosen for the transmitter, you must take care to properly reset and ensure a locked TX programmable divider clock source in coordination with the remainder of the core and system reset sequencing.
• TXOUTCLK frequency (MHz) . Select from among the TXOUTCLK frequencies that can be generated by the TX programmable divider and are compatible with the core configuration and selected device. Options are divided to the required user clock frequencies by the transmitter user clocking network helper block.