UltraScale FPGAs Transceivers Wizard LogiCORE IP Product Guide (PG182) - 1.7 English

Document ID: PG182
Release Date: 2023-05-17
Version: 1.7 English

IP Facts
Introduction
Features
Introduction
Overview
Feature Summary
Applications
Licensing and Ordering Information
Product Specification
Wizard Basic Concepts
Performance
Maximum Frequencies
Other Performance Characteristics
Resource Utilization
Port Descriptions
Reset Controller Helper Block Ports
Transmitter User Clocking Network Helper Block Ports
Receiver User Clocking Network Helper Block Ports
User Data Width Sizing Helper Block Ports
Transmitter Buffer Bypass Controller Helper Block Ports
Receiver Buffer Bypass Controller Helper Block Ports
Transceiver Common Ports
Transceiver Channel Ports
Designing with the Core
General Design Guidelines
Designing with the Helper Blocks
Designing with the Example Design
Reset Controller Helper Block
Reset State Machines
Special GTH Transceiver CPLL Reset Requirements for Engineering Sample (ES1 or ES2) UltraScale Devices
Enabling CPLL Calibration block for UltraScale+ Devices
Reset Sequencing and Other Services
Transmitter User Clocking Network Helper Block
Receiver User Clocking Network Helper Block
User Data Width Sizing Helper Block
Transmitter Module
Receiver Module
Transmitter Buffer Bypass Controller Helper Block
Receiver Buffer Bypass Controller Helper Block
Transceiver Common Primitive
Design Flow Steps
Customizing and Generating the Core
Vivado IDE Customization Parameters
Component Name and Symbol
Basic Tab
System Frame
Transmitter Frame
Transmitter Frame (Advanced Section)
Receiver Frame
Receiver Frame (Advanced Section)
Physical Resources Tab
Free-Running and DRP Clock Frequency (MHz)
TX Master Channel and RX Master Channel
Channel Table and Channel Graphic
Optional Features Tab
Receiver Comma Detection and Alignment Section
Receiver Channel Bonding Section
Receiver Clock Correction Section
Buffer Control Section
Advanced Clocking Section
SATA Section
Structural Options Tab
Helper Block Location Frame
Optional Port Enablement Interface
Constraining the Core
Required Constraints
Core-level Constraints
Example Design Constraints
Out-of-Context Constraints
Device, Package, and Speed Grade Selections
Clock Frequencies
Clock Management
Clock Placement
Banking
Transceiver Placement
I/O Standard and Placement
Other Constraints
Simulation
Synthesis and Implementation
Example Design
Purpose of the Example Design
Hierarchy and Structure
Link Status and Initialization
Link Status Logic
Initialization Module
VIO Core Instance
In-System IBERT Core Instance
Convenience Features
Adapting the Example Design
Limitations of the Example Design
Test Bench
Simulating the Example Design
Simulation Behavior
Migrating and Upgrading
Migrating to the Vivado Design Suite
Upgrading from a Previous Version
Migrating across Devices
Migrating from a Previous Device Family
Debugging
Finding Help with AMD Adaptive Computing Solutions
Documentation
Answer Records
Technical Support
Vivado Design Suite Debug Feature
Additional Resources and Legal Notices
Finding Additional Documentation
Documentation Portal
Documentation Navigator
Design Hubs
Support Resources
References
Revision History
Please Read: Important Legal Notices

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