User State Machine - 2.4 English - PG169

The read and write through the AXI4-Lite slave module interface is controlled by a state machine as shown in the following figure.

The functional description of each state is as follows:

IDLE_STATE

By default the FSM is in IDLE_STATE. When the user_read_req signal becomes High, then the state moves to READ_STATE. Otherwise, when the user_write_req signal is High, it moves to WRITE_STATE.

WRITE_STATE

The user logic provide S_AXI_AWVALID, S_AXI_AWADDR, S_AXI_WVALID, S_AXI_WDATA, and S_AXI_WSTRB in this state to write to the register map through the AXI4-Lite interface. When S_AXI_BVALID and S_AXI_BREADY from the AXI slave are High, then the state moves to ACK_STATE. If there is any write operation happens in any illegal addresses, the S_AXI_BRESP[1:0] indicates 2'b10 that asserts the write error signal to the user logic.

READ_STATE

The user logic provides S_AXI_ARVALID and S_AXI_ARADDR in this state to read from the register map through the AXI4-Lite interface. When S_AXI_RVALID and S_AXI_RREADY are High, then the state moves to ACK_STATE. If there is any read operation happens from any illegal addresses, the S_AXI_RRESP[1:0] indicates 2'b10 that asserts the read error signal to the user logic.

ACK_STATE

The state moves to IDLE_STATE.