GPIO has been provided so that you can control the example design. The I/O ports are shown here.
| Name | Size | I/O | Description |
|---|---|---|---|
| sys_reset | 1 | I | Reset for interlaken_0. |
| gt_ref_clk0_p | 1 | I | Differential input clk to GT. |
| gt_ref_clk0_n | 1 | I | Differential input clk to GT. |
| init_clk | 1 | I | Stable input clk to GT. |
| s_axi_pm_tick | 1 | I | PM tick input for AXI4-Lite read
operations. Note: This input is available
when Include AXI4-Lite Control and Statistics
Interface is selected in the General
tab.
|
| gt_ref_clk1_p | 1 | I | Differential input clk to GT. Applicable only when 25G lane rate for 5 lanes or 6 lanes. |
| gt_ref_clk1_n | 1 | I | Differential input clk to GT. Applicable only when 25G lane rate for 5 lanes or 6 lanes. |
| lbus_tx_rx_restart_in | 1 | I | This signal is used to restart the packet generation and reception for the data sanity test, when the packet generator and the packet monitor are in idle state, that is, when tx_busy_led = 0 and rx_busy_led = 0. |
| simplex_mode_rx_aligned | 1 | I | This signal is used to indicate the generator module that the
Simplex RX module is aligned and generator can now start the packet
generation. Note: This pin is available only
for simplex TX mode.
|
| tx_done_led | 1 | O | Indicates that packet generator has sent all the packets. |
| tx_fail_led | 1 | O | Indicates TX FIFO overflow/underflow error has occurred. |
| tx_busy_led | 1 | O | Indicate that the generator busy, and not able to respond to the lbus_tx_rx_restart_in command. |
| rx_gt_locked_led | 1 | O | Indicates that the GT has been locked. |
| rx_aligned_led | 1 | O | Indicates RX alignment has been achieved. |
Note: For all the input and output signals mentioned in the table,
a three-stage registering is done internally.