TX retransmission logic contains a circular buffer and an optional error injector.
The TX retransmission buffer memory is separate and not integrated into the main IP. It connects to the Integrated Interlaken IP core via a set of RAM ports.
TX retransmission logic contains a circular buffer and an optional error injector.
The TX retransmission buffer memory is separate and not integrated into the main IP. It connects to the Integrated Interlaken IP core via a set of RAM ports.