The integrated IP core for Interlaken uses the transceiver in "RAW mode" by bypassing of the encoder/decoder and gearboxes; but can use the RX elastic buffer.
Also there are restrictions and limitations as to which serial transceivers you can use to implement Interlaken. Following are the rules:
- Interlaken GTs have to be contiguous
- Interlaken on the left column must map to GTs on the left column
- Interlaken on the right column must map to GTs on the right column
- Interlaken must be implemented within an SLR
- Each Interlaken block can only connect to the GT directly adjacent and two up/down quads.
Recommended: For transceiver selections outside of these
rules, contact AMD Technical Support or your local FAE.