| Name | I/O | Description |
|---|---|---|
| Clocking and Resets | ||
| clk | I | All signals between the TX_OOBFC and the user logic are
synchronized to the positive edge of clk. In typical applications, this clock should be tied to the same clock that is used to run the user-side interface of the Interlaken core. |
| clk_tx_ref | I | This clock is used to generate the flow control signals. You are required to supply a clock with a maximum frequency of 200 MHz. The 200 MHz limitation (which is twice the OOBFC clock) is defined by the Interlaken Protocol Definition, Revision 1.2, October 7, 2008. |
| reset | I | Active-High, asynchronous reset input. This signal is automatically synchronized to the appropriate clock domain by the TX_OOBFC. All circuits in the module are reset while this input has a value of 1. This signal must remain asserted until after several clock cycles on both the clk and clk_tx_ref inputs. |
| User-Side Interface – TX_OOBFC Signals | ||
| tx_fc[MAX_CAL-1:0] | I | Input data bus containing the flow control information to be
transmitted by the TX_OOBFC. The width of the bus is set by the
MAX_CAL parameter. Unused bits, as defined by tx_callen_minus1[7:0],
must be tied to 0. Interlaken defines a value of 1 as XON for the corresponding channel, and a value of 0 as XOFF for the corresponding channel. This bus is synchronized to the positive edge of clk. |
| tx_callen_minus1[10|9|8|7:0] | I | This input sets the calendar length for flow control information
for the TX_OOBFC. Allowed values are 0 to MAX_CAL-1. For example,
when MAX_CAL is set to 32, tx_callen_minus1[7:0] can be set to any
value between 0 and 31. It is up to you to ensure that this input is
set correctly. Incorrect setting results in undetermined
behavior. This input should only be changed when reset is asserted (that is, set to 1). Changing the value on this input when not in reset can result in incorrectly transmitted flow-control or status information. This bus is synchronized to the positive edge of clk. |
| tx_lanes_minus1[3:0] | I | This input sets the number of lanes to be included in the Status Message. Allowed values are 0 to 11 (decimal). This value should be set to the number of lanes (minus 1) expected by the receiver. An incorrect setting can result in undetermined behavior. This input should only be changed when reset is asserted (that is, set to 1). This bus is synchronized to the positive edge of clk. |
| tx_intf_status | I | Indicates the health of the interface to be transmitted to the other
device as described in the Interlaken Protocol
Definition, Revision 1.2, October 7,
2008. A value of 1 indicates the interface is healthy. If unused, this input should be a set to a value of 1. This signal is synchronized to the positive edge of clk. |
| tx_lane_status[11:0] | I | Indicates the health of each lane to be transmitted to the other
device as described in the Interlaken Protocol
Definition, Revision 1.2, October 7,
2008. A value of 1 indicates the corresponding lane is
healthy. Bit 0 corresponds to lane 0, bit 1 corresponds to lane 1,
and so on. If unused, all inputs should be a set to a value of 1. This bus is synchronized to the positive edge of clk. |
| tx_err | O | In the event that the clock rates are incorrect for the selected calendar length, the signal tx_err can be asserted to notify the user of this configuration error. |
| tx_status_enable | I | This input can be used to enable and disable the transmission of
the interface and lane status. When this input is a value of 1, tx_intf_status and tx_lane_status operate according to the descriptions. When this input is a value of 0, the values on tx_intf_status and tx_lane_status are ignored, and the interface and lane status are not transmitted. If the transmission of the interface and lane status are not required, this value should be tied to a value of 0. |
| tx_update[31|15|7|3|1|0:0] | O | This output bus indicates when status and flow control information are latched for transmission. If tx_update[0] is asserted, tx_fc[63:0], tx_lane_status, and tx_intf_status bits will be latched at the completion of the current clock cycle; if tx_update[1] is asserted, tx_fc[127:64] will be latched at the end of the current clock cycle; if tx_update[2] is asserted, tx_fc[191:128] will be latched at the end of the current clock cycle and so on. This output bus is synchronized to the edge of clk. |
| Device Interface – TX_OOBFC Signals 1 | ||
| TX_FC_CLK | O (LVCMOS) |
This is the source synchronous clock generated by TX_OOBFC as
defined by the Interlaken protocol. The frequency of this clock is
one-half the frequency of clk_tx_ref. For example, if clk_tx_ref is
200 MHz, this clock is 100 MHz. This signal must be connected directly to a device output pin. |
| TX_FC_DATA | O (LVCMOS) |
The flow control information is transmitted by the TX_OOBFC with
this signal as defined by the Interlaken protocol. This signal must be connected directly to a device output pin. |
| TX_FC_SYNC | O (LVCMOS) |
This signal is used to synchronize the transmitted flow control
information as defined by the Interlaken
Protocol Definition, Revision 1.2, October 7,
2008. This signal must be connected directly to a device output pin. |
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