Data is transferred on a given tx_datain<N> segment when the
corresponding tx_enain<N> is asserted. The
tx_enain<N> signal qualifies other inputs of segment <N> and
must be valid every LBUS clock cycle. When tx_enain<N> is
deasserted, other signals of segment <N> are ignored.
The start of a packet is identified by the assertion of tx_sopin<N>
with the corresponding tx_enain<N>. Similarly, the end of a packet
is identified by the assertion of tx_eopin<N> with the corresponding
tx_enain<N>. Both tx_sopin<N> and
tx_eopin<N> can be asserted on a given cycle. This occurs for
packets that are less than or equal to the LBUS width. Furthermore, both
tx_sopin<N> and tx_eopin<N> can be asserted
for a given segment on a given cycle. This occurs for packets that are less than or
equal to 16 bytes (the segment size).
The channel number for a packet is presented on the tx_chanin<N>
input of the corresponding segment and must be valid for every segment where
tx_enain<N> is asserted. After SOP has been asserted for a
certain channel number, it cannot be asserted again with that channel number until EOP
has been asserted for the same channel number.
The first 16 bytes of a packet must be presented on a given
tx_datain<N> segment during the cycle that the corresponding
tx_sopin<N> and tx_enain<N> are asserted. In
other words, the SOP is segment aligned. Subsequent 16-byte chunks of data are
transferred during segments that follow. For each of those segments, the corresponding
tx_sopin<N> must be negated. The first byte of the packet is
written on Bits[127:120] of the segment, the second byte on Bits[119:112], and so
forth.
The last bytes of the packet are transferred on the tx_datain<N> segment whose corresponding tx_eopin<N> is asserted. Unless tx_eopin<N> is asserted, all 16 bytes of tx_datain<N> must contain valid data whenever tx_enain<N> is asserted. If burst-interleaved mode is
employed, then segments containing data from other packets can be interleaved with
segments containing data for a given packet. The tx_chanin<N> input identifies the packets from different
channels.
During the segment containing the last bytes of a packet, the
tx_mtyin<N> port reflects how many bytes of the corresponding
tx_datain<N> are invalid (or empty). A given
tx_mtyin<N> port only has meaning during cycles when both the
corresponding tx_enain<N> and tx_eopin<N> are
asserted. If tx_mtyin<N> has a value of 0x0, there
are no empty byte lanes (that is, all bits of the segment are valid). If
tx_mtyin<N> has a value of 0x1, then one byte
lane is empty, specifically tx_datain<N>[7:0] does not contain valid
data. If tx_mtyin<N> has a value of 0x2, then two
byte lanes are empty — specifically tx_datain<N>[15:0] does not
contain valid data. If tx_mtyin<N> has a value of
0x3, then three byte lanes are empty — specifically
tx_datain<N>[23:0] does not contain valid data. And so forth for
other possible values of tx_mtyin<N>.
During the segment containing the last bytes of a packet, when
tx_eopin<N> is asserted with tx_enain<N>,
the corresponding tx_errin<N> can also be asserted. This marks the
packet as being in error and this information is included in the final Interlaken
Control Word associated with this packet. When tx_eopin<N> and
tx_errin<N> are sampled as 1, the value of
tx_mtyin<N>[2:0] is ignored and treated as equal to
000, while tx_mtyin<N>[3] is used as usual.
tx_rdyout
Data can be safely written, that is, tx_enain0 asserted, whenever
tx_rdyout is asserted. After tx_rdyout is
negated, additional writes, using tx_enain0, can be safely
performed provided tx_ovfout is never asserted. When
tx_rdyout is asserted again, additional data can be written.
If, at any time, the back-pressure mechanism is violated, the
tx_ovfout is asserted to indicate the violation. Up to eight
write cycles can be safely performed after tx_rdyout is negated,
but no more until tx_rdyout is asserted again.