The disadvantage of a wide non-segmented LBUS is the loss of potential bandwidth that occurs at the end of a packet when the size of the packet is not a multiple of the LBUS width. Therefore, the Interlaken hard block employs the segmented LBUS.
Conceptually, the segmented LBUS is a collection of narrower LBUSes, each 128 bits wide, with multiple transfers presented in parallel during the same clock cycle. Each segment has all the control signals associated with a complete 128-bit LBUS. The 512-bit segmented LBUS has four 128-bit segments with the signals for each segment listed in the following table.
| Segment Number | TX Signals | RX Signals |
|---|---|---|
| 0 | tx_datain0[127:0] tx_chanin0[10:0] tx_enain0 tx_sopin0 tx_eopin0 tx_errin0 tx_mtyin0[3:0] tx_bctlin0 |
rx_dataout0[127:0] rx_chanout0[10:0] rx_enaout0 rx_sopout0 rx_eopout0 rx_errout0 rx_mtyout0[3:0] |
| 1 | tx_datain1[127:0] tx_chanin1[10:0] tx_enain1 tx_sopin1 tx_eopin1 tx_errin1 tx_mtyin1[3:0] tx_bctlin1 |
rx_dataout1[127:0] rx_chanout1[10:0] rx_enaout1 rx_sopout1 rx_eopout1 rx_errout1 rx_mtyout1[3:0] |
| 2 | tx_datain2[127:0] tx_chanin2[10:0] tx_enain2 tx_sopin2 tx_eopin2 tx_errin2 tx_mtyin2[3:0] tx_bctlin2 |
rx_dataout2[127:0] rx_chanout2[10:0] rx_enaout2 rx_sopout2 rx_eopout2 rx_errout2 rx_mtyout2[3:0] |
| 3 | tx_datain3[127:0] tx_chanin3[10:0] tx_enain3 tx_sopin3 tx_eopin3 tx_errin3 tx_mtyin3[3:0] tx_bctlin3 |
rx_dataout3[127:0] rx_chanout3[10:0] rx_enaout3 rx_sopout3 rx_eopout3 rx_errout3 rx_mtyout3[3:0] |
Following is a detailed description of the signals associated with segment 0 of the TX and RX LBUS interfaces. Signals associated with other segments are defined similarly.
tx_datain0[127:0]
Transmit LBUS Data. This bus receives input data from the user logic. The value of the bus
is captured in every cycle for which tx_enain0 is sampled as 1.
tx_chanin0[10:0]
Transmit LBUS channel number. This bus receives the channel number for the packet being
written. The value of the bus is captured in every cycle for which
tx_enain0 is sampled as 1.
In packet mode, the channel number remains the same for the duration of the packet transfer from SOP to EOP. In burst-interleaved mode, the channel number can change for each burst.
tx_enain0
Transmit LBUS enable. This signal is used to enable the TX LBUS Interface. All signals on
the LBUS interface are sampled only in cycles during which tx_enain0 is
sampled as 1.
tx_sopin0
Transmit LBUS Start Of Packet. This signal is used to indicate the SOP when it is sampled
as a 1 and is 0 for all other transfers of the packet. This signal is sampled only in cycles
during which tx_enain0 is sampled as 1.
tx_eopin0
Transmit LBUS EOP. This signal is used to indicate the EOP when it is sampled as a 1 and is
0 for all other transfers of the packet. This signal is sampled only in cycles during which
tx_enain0 is sampled as 1.
tx_errin0
Transmit LBUS Error. This signal is used to indicate a packet contains an error when it is
sampled as a 1 and is 0 for all other transfers of the packet. This signal is sampled only
in cycles during which tx_enain0 and tx_eopin0 are sampled
as 1.
tx_mtyin0[3:0]
Transmit LBUS Empty. This bus is used to indicate how many bytes of the
tx_datain0 bus are empty or invalid for the last transfer of the current
packet. This bus is sampled only in cycles that tx_enain0 and
tx_eopin0 are sampled as 1.
When tx_eopin0 and tx_err0 in are sampled as 1, the value
of tx_mtyin0[2:0] is ignored and treated as if it was 000.
tx_mtyin0[3] is used as usual.
tx_bctlin0
Transmit force insertion of Burst Control word. This input is used to force the insertion
of a Burst Control Word. When tx_bctlin0 and tx_enain0,
are sampled as 1, a Burst Control word is inserted before the data on the
tx_datain0 bus is transmitted even if one is not required to observe the
BurstMax parameter.
This input is used by the enhanced scheduling algorithm, external to the Interlaken IP Core.
rx_dataout0[127:0]
Receive LBUS Data. The value of the bus is only valid in cycles during which
rx_enaout0 is sampled as 1.
rx_chanout0[10:0]
Receive channel number. The bus indicates the channel number of the in-flight packet and is
only valid in cycles during which rx_enaout0 is sampled as 1.
rx_enaout0
Receive LBUS enable. This signal qualifies the other signal of the RX LBUS Interface. The
signals of the RX LBUS Interface are only valid in cycles during which
rx_enaout0 is sampled as 1.
rx_sopout0
Receive LBUS Start of Packet. This signal indicates the SOP when it is sampled as 1 and is
only valid in cycles during which rx_enaout0 is sampled as a 1.
rx_eopout0
Receive LBUS EOP. This signal indicates the EOP when it is sampled as 1 and is only valid
in cycles during which rx_enaout0 is sampled as a 1.
rx_errout0
Receive LBUS Error. This signal indicates that the current packet being received has an
error when it is sampled as 1. This signal is only valid in cycles when both
rx_enaout0 and rx_eopout0 are sampled as a 1. When this
signal is a value of 0, it indicates that there is no error in the packet being
received.
rx_mtyout0[3:0]
Receive LBUS Empty. This bus indicates how many bytes of the rx_dataout
bus are empty or invalid for the last transfer of the current packet. This bus is only valid
in cycles when both rx_enaout0 and rx_eopout0 are sampled
as 1.
When rx_errout0 and rx_enaout0 are sampled as 1, the
value of rx_mtyout0[2:0] is always 000.
rx_mtyout0[3] is used as usual.