The example design provides a quick way to simulate and observe the behavior of the Interlaken core example design projects generated using the Vivado Design Suite.
The currently supported simulators are:
- Vivado simulator (default)
- Mentor Graphics Questa Advanced Simulator (integrated in the Vivado IDE)
- Cadence Incisive Enterprise Simulator (IES)
- Synopsys VCS and VCS MX
The simulator uses the example design test bench and test cases provided along with the example design.
For any project (Interlaken core) generated out-of-the-box, the simulations can be run as follows:
- In the Sources Window, right-click the example project file (.xci), and select Open IP Example Design. The example project is created.
- In the Flow Navigator (left-hand pane),
under Simulation, right-click
Run Simulation and select Run Behavioral
Simulation.Note: The post-synthesis and post-implementation simulation options are not supported for the Interlaken core.
After the Run Behavioral Simulation Option is running, you can observe the compilation and elaboration phase through the activity in the Tcl Console and in the Simulation tab of the Log Window.
- In the Tcl Console, type the run all command and press
Enter. This runs the complete simulation as per the test
case provided in example design test bench.
After the simulation is complete, the result can be viewed in the Tcl Console.
To change the simulators:
- In the Flow Navigator, under Simulation, select Simulation Settings.
- In the Project Settings for Simulation dialog box, change the Target Simulator to QuestaSim/ModelSim.
- When prompted, click Yes to change and then run the simulator.