Revision History - 2.4 English - PG169

• Added a note in the CTL_RX_FORCE_RESYNC port description in Table 2-2.
• Updated IMPORTANT note in the Example Design Hierarchy section in Chapter 5.

• Added IMPORTANT note about sequence multipliers to the Selecting a Sequence Multiplier section in Chapter 3.
• Updated Figures 4-1, 4-2, and 4-3.
• Added the .h Header File subsection to the AXI4-Lite Interface Implementation section in Chapter 5.
• Updated and added many registers n Table 5-7. See Changes from v2.3 to v2.4 in Appendix C for a complete list.

• Updated figures in Chapter 4.
• Added VCU118 IP Integrator board support.
• Added R/LL and R/LH information to the Status and Statistics Register Space section in Chapter 5, Example Design.
• Added gtwiz_reset_tx_datapath and gtwiz_reset_rx_datapath ports in Figures 3-1 and 3-2 and text in Reset section.

• Updated screen displays in Chapter 4.
• Added Simulation Speed Up section to Chapter 4.
• For port changes. See Port Changes in Appendix C.
• For port changes. See Attribute Changes in Appendix C

• Updated Licensing and Ordering Information in Chapter 1.
• Updated screen displays in Chapter 4.
• Removed tx_gt_locked_led from Table 5-2.

• Removed “up to 150” and “Higher speed” from the IP Facts page Introduction.
• Added a bulleted item to the second paragraph of the Transceiver Interface section of Chapter 3.
• Updated much of the text in the Protocol Bypass Interface section of Chapter 3.
• Modified the first three paragraphs of the Protocol Bypass Interface section in Chapter 3.
• Added text to the Important note in the Burst Interleaved Mode section in Chapter 3.
• Added Important note to the tx_rdyout section in Chapter 3.
• Changed the default value to 1 for Bit 3 in Table 5-15, STAT_TX_STATUS_REG.
• Modified the default values for Bit 0 to 1 and Bits 19:8 to 12’hFFF in Table 5-16, STAT_RX_STATUS_REG.
• Modified the default values for Bits 11:0 and Bits 23:1‘2 to 12’hFFF in Table 5-17, STAT_RX_DIAGWORD_REG.
• Modified the default values for Bits 11:0 to 12’hFFF in Table 5-19, STAT_RX_SYNCED_REG.
• Modified the text in the Feature Enhancements in the UltraScale+ Integrated Interlaken IP section of Appendix B.
• Added a reference to PG209 in the References section of Appendix E.
• Changed “protocol bypass” to “Protocol bypass (lane logic only)” throughout.

• Change X signal notation to <N> throughout.
• Updated Figures 4-1 through 4-3.
• Added GT Location section to Table 4-3.
• Updated the Licensing and Ordering Information section in Chapter 1.
• Added Example Design Hierarchy (GT Subcore in Example Design) section to Chapter 5. Example Design.
• Added text to the Retransmission Feature section in Chapter 3.
• Updated the description in the Clocking and Resets section in Appendix D: Debugging.
• Added six new ports to Table 5-3: txdata_in, rxdata_out, tx_clk, rx_clk. axi_gt_reset_all, and axi_gt_loopback.
• Updated the four timing diagrams Figures 5-15 through 5-18.

• Updated the following Figures: 3-1, 3-2, 4-1, 4-2, and 4-3.
• Added gt_drp_done signal to Table 5-3.
• Added the ports and attributes related to Protocol Bypass Mode.

• Added support for UltraScale+ devices.
• Added support for retransmission feature.
• Added references to DS892, DS922, and DS923 data sheets.
• Added DRP_CLK to the Clock Domain column for the DRP Path/Control Signals in Table 2-2.
• Changed reserved port descriptions in Table 2-2 to be retransmission interface ports. See Port Changes in Appendix C, Migrating and Updating.
• Changed reserved attribute descriptions to be retransmission attributes in Table 2-3. See Attribute Changes in Appendix C, Migrating and Updating.
• Updated Figure 3-1, Figure 3-2, Figure 4-1, Figure 4-2, Figure 4-3.
• Added the Protocol Bypass Interface and Retransmission Interface sections to Chapter 3.
• Added Table 3-7, DRP Address Map of the ILKN block in UltraScale+ Devices.
• Modified Packet Mode and Burst Interleaved Mode sections in Chapter 3. Completely BurstMin Requirements, Configuring the TX Retransmission Buffer Depth, Selecting a Sequence Multiplier, and Measuring Request-to-Discontinuity Latency sections.
• Completely revised TX Transactions and RX LBUS Interface sections in Chapter 3.
• Changed CORE_CLK to LBUS_CLK in CRC32 Diagnostics Checking and Transmitter Multiple-Use Bits sections. Added rx_mubits_updated description.
• Changed CTL_TX_FC_STAT[MAX_CALLEN-1:0] to CTL_TX_FC_STAT[MAX_CALLEN-1:255].
• Updated CTL_TX_FC_CALLEN[3:0] description In Table 4-1, added GT DRP/Init Clock parameter and removed AXI4-Lite Interface section.
• Updated most all of Table 4-2, Table 4-3 and Table 5-3. Added s_axi_pm_tick to Table 5-2.
• Added S_AXI_PM_TICK to Table 5-4.
• Added some text to Status and Statistics Register Space section.
• Updated defaults in Table 5-8 and Table 5-9.

• Added description to examples section that illustrates LBUS cycles.
• Updated Figure 3-4.
• Added additional description to RX LBUS Interface section.

Design Flow Steps Chapter:

• Updated Vivado IDE core customization screen captures.
• Added Include AXI4-Lite Control and Statistics Interface option to the Configuration Options tab.

Out-of-Band Flow Control Appendix:

• Changed resetn to reset.
• In the TX_OOBFC Pin List table:
  • Changed tx_lanes_minus1[LANES_LOG2-1:0] to tx_lanes_minus1[3:0].
  • Changed tx_lane_status[LANES-1:0] to tx_lane_status[11:0].
  • Added tx_status_enable.
• In the RX_OOBFC Pin List table:
  • Changed rx_lane_status[LANES-1:0] to rx_lane_status[11:0].
  • Added rx_force_xoff_if_crcerr.
  • Removed resetn_RX_FC_CLK.

Debugging Appendix:

• Added information about performance to Protocol Debug section.

• Added domain information to port description table.
• Updated the Clocking Reset Interface tables for Synchronous Mode and Asynchronous Mode.
• Updated to the Vivado IDE core customization options.
• Removed User Parameter section content.
• Example Design chapter:
  • Updated the example design hierarchy diagram, and design details.
  • Added the Core XCI Top-Level Ports section.
  • Added the AXI4-Lite Interface Implementation section.

• Updated document title. Moved performance and resource utilization data to www.xilinx.com.
• Updated the Clocking Reset Interface tables for Synchronous Mode and Asynchronous Mode.
• Updated Vivado IP catalog options/User Parameters for core v1.6:
  • Added new Protocol Bypass Mode and Disable Skipword parameters.
  • Added new Line Rate value. indicated that Out-of-Band Flow Control is now grayed out.
  • Added Enable Rate Limiter description.
  • Added Max Token Count description, default range.
  • Added Delta Token Count description, default range; updated values.
  • Added Update Interval description, default range.
  • Added Enable Error Injection description.
• Updated the Invalid Segment LBUS Cycles table.
• Updated the Example Design Hierarchy, and Example Design Hierarchy with Shared Logic Implementation tables.
• Updated the Interlaken Support Modes and Configurations table.
• Updated Vivado Lab Edition to Vivado Design Suite debug feature.

• Updated resource utilization information.
• Vivado IDE parameter additions, and updates.
• Updated example design details, added new user interface ports, and added Simplex TX and RX mode simulation information.
• Updated Vivado lab tools to Vivado Lab Edition.

• Updated to v1.4 of the core.
• Updated Typical Clock Frequencies for Each Interlaken Configuration table with new line rate and refclk rates.
• Vivado IDE parameter additions and updates.
• Included information regarding retransmission not being supported in this core version.

• Updated to v1.3 of the core. Added clocking reset diagrams.
• Added new parameters: Low Latency Mode, Enable Retransmission, Number of RAM Banks, Buffer Depth, Sequence Multiplier (TX), Sequence Multiplier (RX), Watchdog Timer, Long Timer, Retry Timer, Wrap Around Timer, Lane 00 to Lane 11.
• Added values for existing parameters: Line Rate, GT Ref Clk, Channel Topology.
• Updated user parameters table.
• Updated example design information.
• Updated out-of-band flow control information.
• Added simulation, hardware, interface, and protocol debug information.

• Updated to v1.2 of the core.
• Added out-of-band flow control information.
• Added user parameters table.

• Added DRP information.
• Updated Figures 2-1, 4-1, 4-2, 4-3, 5-1, 5-5, and 5-6.
• Added performance and resource material.
• Updated transceiver interface rules.
• Updated the constraints information.
• Added new transceiver_debug and GT_common module text.
• Added shared logic implementation section. Added information about simulating, synthesizing, and implementing the example design.