The Integrated Interlaken IP core has separate reset inputs for the RX and TX paths that can be asserted independently. Within the RX and TX paths, there are resets for each of the various clock domains. The reset procedure is simple and the only requirement is that a reset must be asserted when the corresponding clock is stable. The Interlaken core takes care of ensuring the different resets properly interact with each other internally and the interface operates properly (that is, there is no order required for asserting/deasserting different resets). The core must be held in reset until the corresponding clock is fully stable.
The Integrated Interlaken IP core provides sys_reset input to reset the
GTs and integrated Interlaken block and gtwiz_reset_tx_datapath and
gtwiz_reset_rx_datapath to reset the GT and Interlaken RX and TX datapaths
individually.
Some of the attributes to the Integrated Interlaken IP core core can only be modified while the core is held in reset. If one of these attributes needs changing, the appropriate RX or TX LBUS reset input (RX_RESET or TX_RESET) must be asserted until the control input is stabilized. The core has several reset inputs. All resets must be, asynchronously asserted, and synchronously deasserted.
The reset and clocking scheme selected for the core depends on how the TX and RX logic are
clocked by the GT output clocks. In synchronous clock mode, both the TX and RX helper blocks
are clocked with the same GT output clock, txoutclk_out[0]. In asynchronous
clock mode, TX and RX helper blocks are clocked with txoutclk_out[0] and
rxoutclk_out[0] clock outputs from the GT, respectively.
The selection between these modes is made in the Vivado Design Suite. For more information, see Design Flow Steps. The following figures show the clocking reset diagrams for the asynchronous and synchronous clock modes of the Interlaken core.